9FGP202A datasheet(8/19 Pages) IDT

Part #	9FGP202A

Description	FREQUENCY TIMING GENERATOR FOR PERIPHERALS

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Manufacturer	IDT [Integrated Device Technology]

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9FGP202A

FREQUENCY TIMING GENERATOR FOR PERIPHERALS

IDT®

FREQUENCY TIMING GENERATOR FOR PERIPHERALS

8

9FGP202A

REV D 070511

Electrical Characteristics–Input/Supply/Common Output Parameters

P ARAMETE R

SYMB OL

CONDITIONS*

MIN

TYP

MAX

UNITS

Notes

Input High Voltage

VIH

3.3 V +/-5%

2

VDD + 0.3

V

1

Input Low Voltage

V

IL

3.3 V +/-5%

V

SS - 0.3

0.8

V

1

Input High Current

I

IH

V

IN = V DD

-5

5

uA

1

IIL1

VIN = 0 V; Inputs with no pull-up

resistors

-5

uA

1

IIL2

VIN = 0 V ; Inputs with pull-up

resistors

-200

uA

1

Low Thresh old Input-

High Voltage

VIH_FS

3.3 V +/-5%

0.7

VDD + 0.3

V

1

Low Thresh old Input-

Low Voltage

V IL_FS

3.3 V +/-5%

VSS - 0.3

0.35

V

1

Operating Current

IDD3.3OP

all outputs driven

200

mA

1

all diff pairs driven

30

mA

1

all differential pairs tri-stated

8

mA

1

Input Frequency

F

i

V

DD = 3.3 V

25.00000

MHz

2

Pin Inductance

L

pi n

7nH

1

CIN

Logic Inputs

4

pF

1

COUT

Output pin capacitance

5

pF

1

CINX

X1 & X 2 pins

5

pF

1

Clk Stabiliza tion

TSTAB

From V DD Power-Up or de-

assertion of PD to 1st clock

2.5

ms

1

Modulation Frequency

Triangular Modulation

30

33

kHz

1

Tdrive_PD

CP U output enable after

PD de-assertion

300

us

1

Tfall_ PD

PD fall time of

5

ns

1

Trise_PD

PD rise time of

5

ns

1

SMBus Voltage

VDD

2.7

5.5

V

1

Low-level Output Voltage

V

OL

@ I

PUL LUP

0.4

V

1

Current sinking at

V

OL = 0.4 V

IPULLUP

4mA

1

SCLK/SDATA

Clock/Data Rise Time

T

RI2C

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000

ns

1

SCLK/SDATA

Clock/Data Fall Time

TFI2C

(Min V IH + 0.15) to

(Max VIL - 0.15)

300

ns

1

*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%

1Guaranteed by design and characterization, not 100% tested in production.

2 Input frequ ency should be measured at the REF pin and tuned to ideal 25.00MHz to meet ppm frequency accuracy on PLL outputs.

Input L ow Current

Powerdown Current

IDD3.3PD

Input Capacitance

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