—7—

CXD2434ATQ

3) Phase conditions of HD, VD, TRIG, EFS and ESG

CL

HD, VD, TRIG

EFS, ESG

Symbol

Definition

HD, VD, TRIG, EFS and ESG setup time, activated by CL

HD, VD, TRIG, EFS and ESG hold time, activated by CL

Min.

20

5

Typ.

Max.

Unit

ns

ns

4) Phase characteristics of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID

CL

XV1, XV2, XV3

BUSY, WEN, ID

XSG, PBLK,

XCPDM, XCPOB

load capacitance of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID=10 pF

Symbol

Definition

XV1, XV2 and XV3 delay, activated by the falling edge of CL

BUSY, WEN and ID delay, activated by the rising edge of CL

XSG, PBLK, XCPDM and XCPOB delay, activated by the

rising edge of CL

Min.

30

40

40

Typ.

Max.

65

60

55

Unit

ns

ns

ns