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IS31IO7328 Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc |
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IS31IO7328 Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc |
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10 / 15 page  IS31IO7328 Integrated Silicon Solution, Inc. – www.issi.com 10 Rev.A, 12/27/2011 START AND STOP CONDITIONS Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, the master issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (see Figure 4). BIT TRANSFER One data bit is transferred during each clock pulse. The data on SDA must remain stable while SCL is high (Figure 5). Figure 6 Acknowledge 12 34 5 6 78 1 234 5 678 12 3 4 5 6 7 8 SCL START CONDITION R/W ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE Slave Address 0 Command Byte Data Nibble 0 0 0 0 SDA INTERNAL WRITE TO PORT DATA OUT FROM PORT tPV DATA VALID S A A A Write 0 When Writing The Port Figure 7 Writing to the IS31IO7328 1 2 3 4 567 8 123 4 5 6 78 ACKNOWLEDGE FROM SN7328 1 S ANA 10 1 1 0 AD 0 D7 D6 D5 D4 D3 D2 D1 D0 NO ACKNOWLEDGE FROM MASTER P PORT I/O Ineffective Data 1 2 3 4 56 78 1234 5 67 8 SCL ACKNOWLEDGE FROM SN7328 0 SA A 10 1 1 0 AD 0 Command Byte ACKNOWLEDGE FROM SN7328 W tIV PORT INT OUTPUT R S=START CONDITION P=STOP CONDITION SHADED=SLAVE TRANSMISSION NA=NO ACKNOLEDGE tPSU tIR tPH SDA Effective Data Figure 8 Reading I/O Ports of IS31IO7328 Note: Data from/to IS31IO7328, only the 4 MSBs of the data are effective |
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