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CXD2300Q

2. This IC uses an offset cancel type comparator and the comparator operates synchronously with an

external clock. These modes are respectively indicated on the timing chart with S, H, C symbols. That is,

the comparator performs input sampling (auto zero) mode, input hold mode and comparison mode using

the external clock.

3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled

with the falling edge of the first clock by means of the upper comparator block and the lower comparator A

block.

The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock.

Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to

the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the

second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock.

Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.

Operation Notes

1. Power supply and ground

To reduce noise effects, separate the analog and digital systems close to the device. For both the digital

and analog power supply pins, use a ceramic capacitor of about 0.1 µF set as close as possible to the pin

to bypass to the respective grounds.

2. Analog input

Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.

However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.

When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be

prevented by inserting a resistance of about 100

Ω in series between the amplifier output and A/D input.

3. Clock input

The clock line wiring should be as short as possible also, to avoid any interference with other signals,

separate it from other circuits.

4. Reference input

VRB pins to analog ground, by means of a capacitor about 0.1 µF, the stable characteristics of the

reference voltage are obtained. By shorting VRT and VRTS, VRB and VRBS, the self-bias function that

5. Timing

Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks

and with the following rising edge. The delay from the clock rising edge to the data output is about 18 ns.

6. OE pin

obtained.