IS61DDB41M18A

IS61DDB451236A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. 00A

7/05/2012

4

SRAM Features description

Block Diagram

Data

Register-

Burst4

Control

Logic

17 (18)

Addresses :

SA

4 (2)

LD#

R/W#

Clock

Generator

K

K#

512K x 36

(1M x 18)

Memory Array

Write

Driver

Select Output Control

19 (20)

36x4 (18x4)

36x4

(18x4)

36 (18)

DQ(Data-out

&Data-In)

CQ, CQ#

(Echo Clocks)

C#

C

Add Reg &

Burst

Control

144

(72)

Output

Reg

36

(18)

36(18)

2

36x4 (18x4)

Note: Numerical values in parentheses refer to the x18 device configuration.

Read Operations

The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R/W# in active high

state at the rising edge of the K clock. R/W# can be activated every other cycle because two full cycles are required to

complete the burst-of-four read in DDR mode. A second set of clocks, C and C#, are used to control the timing to the

outputs. A set of free-running echo clocks, CQ and CQ#, are produced internally with timings identical to the data-outs.

The echo clocks can be used as data capture clocks by the receiver device.

When the C and C# clocks are connected high, the K and K# clocks assume the function of those clocks. In this case,

the data corresponding to the first address is clocked one and half cycles later by the rising edge of the K# clock. The

data corresponding to the second burst is clocked two cycles later by the following rising edge of the K clock. The third

data-out is clocked by the subsequent rising edge of the K# clock, and the fourth data-out is clocked by the

subsequent rising edge of the K clock.

Whenever LD# is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD# is high)

does not terminate the previous read. The output drivers disable automatically to a high state.

Write Operations

Write operations can also be initiated at every other rising edge of the K clock whenever R/W# is low. The write

address is also registered at that time. When the address needs to change, LD# needs to be low simultaneously to be

registered by the rising edge of K. Again, the write always occurs in bursts of four.