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CXD1804AR Datasheet(PDF) 3 Page - Sony Corporation |
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CXD1804AR Datasheet(HTML) 3 Page - Sony Corporation |
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3 / 103 page  – 3 – CXD1804AR Block Diagram 47 39 43 40 26 28 32 31 45 65 64 63 62 119 120 121 50 141 142 143 144 122 123 to 129 131 to 138 51 to 57, 59 to 61 68 to 75, 77 to 84 3 • 5 • 8 • 10 • 11 • 15 • 18 • 20 • 23 CD-ROM Decoder Block SCSI Controller Block sub CPU I/F Descrambler Sync Control Priority Resolver FIFO Control 16byte FIFO 24bit Transfer Byte Counter Clock Gen. Microcode ROM Microcode Core & Registers Arbitration Selection SCSI Phase Ctrl SCSI Handshake Buffer Handshake Buffer Address Gen. DMA Sequencer Subcode Deinterleave & ECC Main Data Error Correction MA (0:9) MDB (0:15) XMWR XUCAS XLCAS XCAS EXCK SBIN SCOR WFCK C2PO BCLK MDAT LRCK DATO XLAT DSTB XDB (0:7) XDBP XREQ XACK XRST XBSY XATN XSEL XCD XMSG XIO D (7:0) A (0:6) XWAT XTL2 CLK XTL1 XRES XCS XWR INT XRD 87 88 89 90 91 92 93 94 98 99 100 CD DSP I/F |
Similar Part No. - CXD1804AR |
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Similar Description - CXD1804AR |
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