– 6 –

CXD1257AR

2. Changes in I/O Signals in Each Mode

Symbol

GM

D2

TEST2

XSP1

XSP2

XSH1

XSH2

XDL1

XDL2

BFG

CLP2

CLP3

ID

55

12

36

41

42

43

44

45

46

47

49

50

53

L

L

L

Color separation

sample-and-hold

pulse output

Color separation

sample-and-hold

pulse output

Switching sample-

and-hold pulse

output

Switching sample-

and-hold pulse

output

Delay line clock

Delay line clock

Burst flag gate

pulse output

Clamp pulse output

Clamp pulse output

Line identification

output

H

L

L

Halted at High

Halted at High

Halted at Low

Halted at Low

Halted at High

Halted at Low

Burst flag gate

pulse output

(normally not used)

Standby control input

Low: Standby

High: Normal

operation

Standby control∗

Low: All circuits

halted for

standby mode

High: Only CL

output for

standby mode

Line identification

output

H

L

H

Color separation

sample-and-hold

pulse output

Color separation

sample-and-hold

pulse output

Switching sample-

and-hold pulse

output

Switching sample-

and-hold pulse

output

Halted at High

Halted at Low

Burst flag gate

pulse output

(normally not used)

Standby control input

Low: Standby

High: Normal

operation

Standby control∗

Low: All circuits

halted for

standby mode

High: Only CL

output for

standby mode

Line identification

output

Pin No.

Analog color

Digital color 1

Digital color 2

∗ When CLP2 = High, normal operation occurs regardless of whether CLP3 is high or low.

(Mode combinations other than those shown above cannot be used.)

Note) In the standby mode described above, XCK, XSG1, XSG2, XV1, XV2, XV3, XV4, XSUB, H1, H2, RG,

XSHD, XSHP, XSP1, XSP2, XSH1, XSH2, XDL1, and XDL2 pins are halted at Low. MCK, CLP1, CLP4,

PBLK, ID, XVCT, WEN, BFG, A0, A1, A2, A3, A4, and A5 pins are halted at the state just before

standby.