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CXB1583Q Datasheet(PDF) 5 Page - Sony Corporation |
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CXB1583Q Datasheet(HTML) 5 Page - Sony Corporation |
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5 / 23 page  – 5 – CXB1583Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description 32 PCLKOUT0 TTL output TTL level Receive byte clock 0 output. This clock is used to take the parallel data (PDO0 to 9) at the next-stage system. VEET VCCT TTL-OUT 31 PCLKOUT1 TTL output TTL level 34 RXLKDT TTL output TTL level Receive byte clock 1 output. PCLKOUT0 inverted clock. RX_PLL lock detection signal output. Outputs high level when the PLL is locked to the serial data or the serial data has no signal; Outputs low level when the PLL is not locked. RXLKDT output may sporadically go high when the PLL starts to lock to the serial data. 35 TXLKDT TTL output TTL level TX_PLL lock detection signal output. Outputs high level when the PLL is locked to REFCLK and operating normally; Outputs low level when the PLL is not operating normally. VEET VCCT TTL-OUT VEET VCCT TTL-OUT VEET VCCT TTL-OUT |
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