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CXA3218N

(2) FM demodulation circuit

The FM demodulation circuit is a PLL demodulator which consists of an oscillator (OSC.), phase

discriminator and DCAMP. The oscillator resonance circuit is connected to OSCB1 to OSCB2 (Pins 19 to

22) and the loop filter to LPFN (Pin 23) and LPFP (Pin 24). The DCAMP differential output comes from

VCODR2 (Pin 16) and VCODR1 (Pin 17), and this output is used as the drive voltage for the varicap that

comprises the oscillator.

(3) Detection signal amplification circuit

The signal which is detected by the FM demodulation circuit is amplified at DETAMP circuit and then

output from DETOUT (Pin 7). The gain of this amplification circuit can be adjusted by the voltage applied

to GCONT (Pin 9).

(4) AFT circuit

The AFT circuit detects the frequency error in the 2nd IF signal as a voltage displacement from the FM

demodulation signal input to the AFT block, and outputs the two values of High (5 V) or Low (0 V) from

AFTDWN (Pin 10) and AFTUP (Pin 11). High indicates the frequency change command (active-High).

Furthermore, the High output from both pins indicates the dead zone. The LPF capacitor is connected to

ANA (Pin 12) and the keyed pulse for the keyed AFT is input to KEYEDIN (Pin 13). The KEYEDIN (Pin 13)

voltage should be 0 V during mean AFT value. The sample-and-hold capacitors are connected to SH2

(Pin 14) and SH1 (Pin 15).

Apply the offset adjustment voltage to OFFSET (Pin 6) to cancel the effects of the DC offset in the IC.

(5) Other

A capacitor is connected to eliminate the regulator voltage noise to VREG (Pin 8), and use this output as

the reference voltage for internal adjustment.