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CXA3185/3186N

Description of PLL Block

The PLL on this IC supports the 3-wire bus control format.

The serial data is input to the DA, CL and CE pins. The data is loaded to the shift register at the clock rise,

and latched at the enable fall.

1) Mode Setting Method

The modes for each frequency step are set according to the MS pin voltage.

Symbol

CE

CL

DA

LOCK

3-wire bus control

Enable input

Clock input

Data input

Lock signal output

Mode

A-0

A-1

A-2

A-3

A-4

MS pin voltage

OPEN

Main

divider

15 bit

14 bit

15 bit

15 bit

15 bit

Reference

divider

1024

512

640

512

512

Reference

frequency∗

3.90625 kHz

7.8125 kHz

6.25 kHz

7.8125 kHz

7.8125 kHz

Frequency

step∗

31.25 kHz

62.5 kHz

50 kHz

62.5 kHz

62.5 kHz

Control

word length

Total 19 bits

Total 18 bits

Total 19 bits

Total 19 bits

Total 27 bits

∗ Frequency step is for when X’tal OSC = 4 MHz.

2) Programming

• The VCO lock frequency is obtained according to the following formula.

fosc = fref

× 8 × (32 M + S)

fosc : local oscillator frequency

fref : reference frequency

8

: prescaler fixed frequency division ratio

M

: main divider frequency division ratio

S

: swallow counter frequency division ratio

The variable frequency division ranges of M and S are as follows, and are set as binary.

32

≤ M ≤ 1023 (32 ≤ M ≤ 511 for A-1 mode)

0

≤ S ≤ 31

• The PLL control data is comprised of the above frequency data and the band switch control data.