NCV7420

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11

Table 13. DC CHARACTERISTICS, SUPPLY − Pin VBB

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Ibb_ON

Supply current

Normal mode; LIN recessive

1.6

mA

Ibb_STB

Supply current

Stand−by mode,

Vbb = 6–18 V,

70

mA

Ibb_SLP

Supply current

Sleep mode, Vbb = 6–18 V,

20

mA

Table 14. DC CHARACTERISTICS, VOLTAGE REGULATOR − Pin VCC

Vcc_out

Regulator output voltage

Vcc load 1 mA − 30 mA

4.9

5.0

5.1

V

Vcc load 0 mA − 50 mA

4.83

5.0

5.17

Iout_max_abs

Absolute maximum output current

Thermal shutdown must be

taken into account

50

mA

Iout_lim

Over−current limitation

50

100

170

mA

DVcc_out

Line Regulation (Note 26)

Vbb 6−26 V, Iout = 5 mA,

Tj = 25°C

0.9

mV

Load Regulation (Note 26)

Iout 1−50 mA, Vbb = 14 V,

Tj = 25°C

74

mV

Vdo

Dropout Voltage (Vbb−Vcc_out)

Figure 19 (Notes 25, 26)

Iout = 1 mA, Tj = 25°C

13

mV

Iout = 10 mA, Tj = 25°C

136

mV

Iout = 50 mA, Tj = 25°C

794

mV

Table 15. DC CHARACTERISTICS LIN TRANSMITTER − Pin LIN

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VLin_dom_LoSup

LIN dominant output voltage

TXD = low; Vbb = 7.3 V

1.2

V

VLin_dom_HiSup

LIN dominant output voltage

TXD = low; Vbb = 18 V

2.0

V

Vser_diode

LIN Voltage drop at serial diode (Note 21)

TXD = high; Ilin = 10 mA

0.3

1

V

ILIN_lim

Short circuit current limitation

VLin = Vbb_max

40

200

mA

Rslave

Internal pull−up resistance

20

33

47

kW

CLIN

Capacitance on pin LIN (Note 23)

15

25

pF

ILIN_off_dom

LIN output current bus in dominant state

Driver off; Vbb = 12 V

−1

mA

ILIN_off_rec

LIN output current bus in recessive state

Driver off; Vbb < 18 V

Vbb < VLin < 18 V

1

mA

ILIN_no_GND

Communication not affected

Vbb = GND = 12 V;

0 < VLin < 18 V

−1

1

mA

ILIN_no_Vbb

LIN bus remains operational

Vbb = GND = 0 V;

0 < VLin < 18 V

5

mA

Table 16. DC CHARACTERISTICS LIN RECEIVER − Pin LIN

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Vbus_dom

Bus voltage for dominant state

0.4

Vbb

Vbus_rec

Bus voltage for recessive state

0.6

Vbb

Vrec_dom

Receiver threshold

LIN bus recessive → dominant

0.4

0.6

Vbb

21.The voltage drop in Normal mode between LIN and VBB pin is the sum of the diode drop and the drop at serial pull up resistor. The drop

at the switch is negligible. See Figure 1.

22.By one of the trimming bits, following reconfiguration can be done during chip−level testing in order to fit the NCV7420_5 into different

interface: pins TxD and EN will have typ. 10 kW pull−down resistor to ground and pin WAKE will have typ. 10 mA pull−up current source.

23.Guaranteed by design. Not tested.

24.Vbb under−voltage threshold is always higher than Vbb POR low level (Vbb_UV_th > PORL_VBB)

25.Measured at output voltage Vcc_out = (Vcc_out@Vbb = 6 V) – 2%.

26.Values based on design and characterization. Not tested in production.