CY14C101Q

CY14B101Q

CY14E101Q

Document Number: 001-54393 Rev. *I

Page 3 of 33

Pinouts

Figure 1. 8-pin SOIC pinout [1, 2, 3]

Figure 2. 16-pin SOIC pinout

HOLD

SCK

1

2

3

4

5

CS

8

7

6

VCC

SI

SO

WP

Top View

not to scale

CY14X101Q1A

VSS

HOLD

SCK

1

2

3

4

5

CS

8

7

6

VCC

SI

SO

Top View

not to scale

CY14X101Q2A

V

CAP

VSS

NC

V

WP

VCAP

1

2

3

4

5

6

7

8

9

10

11

12

13

NC

16

15

14

VCC

SO

SI

SCK

CS

HSB

NC

NC

NC

HOLD

NC

Top View

not to scale

SS

CY14X101Q3A

Pin Definitions

Pin Name [1, 2, 3]

I/O Type

Description

CS

Input

Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low

power standby mode.

SCK

Input

this clock. Serial output is driven at the falling edge of the clock.

SI

Input

Serial Input. Pin for input of all SPI instructions and data.

SO

Output

Serial Output. Pin for output of data through SPI.

WP

Input

Write Protect. Implements hardware write protection in SPI.

HOLD

Input

HOLD Pin. Suspends Serial Operation.

HSB

Input/Output

Hardware STORE Busy:

Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE

a weak internal pull up resistor keeps this pin HIGH (External pull up resistor connection optional).

Input: Hardware STORE implemented by pulling this pin LOW externally.

Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the

SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It

must never be connected to ground.

NC

No connect

No Connect: This pin is not connected to the die.

Power supply Ground

Power supply Power supply

Notes

1. HSB pin is not available in 8-pin SOIC packages.

3. CY14X101Q2A part does not have WP pin.