CY7C4221 / CY7C4231

Document Number: 38-06016 Rev. *H

Page 6 of 22

Figure 2. Offset Register Location and Default Values

Programmable Flag (PAE, PAF) Operation

Whether the flag offset registers are programmed as described

in Table 1 or the default values are used, the programmable

almost-empty flag (PAE) and programmable almost-full flag

(PAF) states are determined by their corresponding offset

registers and the difference between the read and write pointers.

The number formed by the empty offset least significant bit

register and empty offset most significant register is referred to

as n and determines the operation of PAE. PAE is synchronized

to the LOW-to-HIGH transition of RCLK by one flip-flop and is

LOW when the FIFO contains n or fewer unread words. PAE is

set HIGH by the LOW-to-HIGH transition of RCLK when the

FIFO contains (n + 1) or greater unread words.

The number formed by the full offset least significant bit register

and full offset most significant bit register is referred to as m and

determines the operation of PAF. PAF is synchronized to the

LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW

when the number of unread words in the FIFO is greater than or

equal to CY7C4221 (1K – m) or CY7C4231 (2K – m). PAF is set

HIGH by the LOW-to-HIGH transition of WCLK when the number

of available memory locations is greater than m.

1K × 9

2K × 9

8

0

8

0

8

0

8

0

(MSB)

00

(MSB)

00

7

1

7

1

8

0

8

0

8

0

8

0

(MSB)

000

(MSB)

000

7

2

7

2

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

Table 1. Writing the Offset Registers

LD WEN

WCLK [1]

Selection

0

0

Empty offset (LSB)

Empty offset (MSB)

Full offset (LSB)

Full offset (MSB)

0

1

No operation

1

0

Write into FIFO

1

1

No operation

Table 2. Status Flags

Number of Words in FIFO

FF

PAF PAE

EF

CY7C4221

CY7C4231

0

0

H

H

L

L

1 to n[2]

1 to n[2]

H

H

L

H

(n + 1) to 512

(n + 1) to 1024

H

H

H

H

513 to (1024 – (m + 1))

1025 to (2048 – (m + 1))

H

H

H

H

(1024–m)[3] to 1023

(2048 – m)[3] to 2047

H

L

H

H

1024

2048

L

L

H

H

Notes

1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.

2. n = Empty Offset (n = 7 default value).

3. m = Full Offset (m = 7 default value).