NB7VQ572M

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3

Table 2. PIN DESCRIPTION

Pin Number

Pin Name

I/O

Pin Description

1, 4

5, 8

25, 28

29, 32

IN0, IN0

IN1, IN1

IN2, IN2

IN3, IN3

LVPECL, CML,

LVDS Input

Noninverted, Inverted, Differential Clock or Data Inputs

2, 6

26, 30

VT0, VT1

VT2, VT3

Internal 100 W Center−tapped Termination Pin for INx / INx

15

18

SEL0

SEL1

LVTTL/LVCMOS

Input

Input Select pins, default HIGH when left open through a 94 kW pullup resistor. Input

14, 19

NC

−

No Connect

10, 13, 16

17, 20, 23

−

Positive Supply Voltage.

11, 12

21, 22

Q0, Q0

Q1, Q1

CML Output

Inverted, Non−inverted Differential Outputs.

9, 24

GND

Negative Supply Voltage

3

7

27

31

VREFAC0

VREFAC1

VREFAC2

VREFAC3

−

Output Voltage Reference for Capacitor−Coupled Inputs

−

EP

−

The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the

die for improved heat transfer out of package. The exposed pad must be attached to

a heat−sinking conduit. The pad is electrically connected to the die, and must be

electrically connected to GND.

1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or left

open, and if no signal is applied on INx/INx input, then the device will be susceptible to self−oscillation.