6-11 GHz Variable Gain Amplifier

CHA4861-QGG

Ref. : DSCHA4861-QGG2262 - 18 Sep 12

11/14

Specifications subject to change without notice

Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France

Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34

Definition of the Sij reference planes

The

reference

planes

used

for

Sij

measurements given above are symmetrical

from the symmetrical axis of the package

(see drawing beside). The input and output

reference planes are located at 3.66mm

offset

(input

wise

and

output

wise

respectively) from this axis. Then, the given

Sij parameters incorporate the land pattern of

the evaluation motherboard recommended in

paragraph "Evaluation mother board".

Notes

Due to ESD protection circuits on RF input and output, an external capacitance might be

requested to isolate the product from external voltage that could be present on the RF

accesses.

ESD protections are also implemented on gate and control accesses.

The DC connections do not include any decoupling capacitor in package, therefore it is

mandatory to provide a good external DC decoupling (10nF) on the PC board, as close as

possible to the package.