PCA6416A datasheet(6/42 Pages) NXP

Part #	PCA6416A

Description	Low-voltage translating 16-bit I2C-bus/SMBus I/O expander

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PCA6416A

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Product data sheet

Rev. 1 — 11 September 2012

6 of 42

NXP Semiconductors

PCA6416A

Low-voltage translating 16-bit I2C-bus/SMBus I/O expander

6.

Voltage translation

Table 4 shows how to set up VDD levels for the necessary voltage translation between the

I2C-bus and the PCA6416A.

7.

Functional description

Refer to Figure 1 “Block diagram (positive logic)”.

7.1 Device address

The address of the PCA6416A is shown in Figure 6.

ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW

(logic 0) to assign one of the two possible slave addresses. The last bit of the slave

address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1)

selects a read operation, while a LOW (logic 0) selects a write operation.

Table 4.

Voltage translation

VDD(I2C-bus) (SDA and SCL of I2C master)

VDD(P) (Port P)

1.8 V

2.5 V

1.8 V

3.3 V

1.8V

5V

2.5 V

1.8 V

2.5 V

3.3 V

2.5V

5V

3.3 V

1.8 V

3.3 V

2.5 V

3.3 V

3.3V

5V

1.8V

5V

2.5V

5V

3.3V

5V

Fig 6.

PCA6416A address

R/W

002aah045

0

1

0

AD

DR

fixed

slave address

hardware selectable

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