LE24512AQF

No.A2087-6/14

Functional Description

The device supports the I

device that reads the data to a receiver. The device that controls the data transfer is known as the bus master, and the

other as the slave device.

1 Start condition

A start condition needs to start the EEPROM operation, it is to set falling edge of the SDA while the SCL is stable in

the high status.

2 Stop condition

A start condition is identified by rising edge of the SDA signal while the SCL is stable in the high status. The device

becomes the standby mode from a read operation by a stop condition. In a write sequence, a stop condition is trigger

to terminate the write data inputs and it is trigger to start the internal write cycle. After the internally write cycle time

which is specified as tWC, the device enters a standby mode.

3 Data input

During data input, the device latches the SDA on the rising edge of the SCL. For correct the operation, the SDA must

be stable during the rising edge of the SCL.

4 Acknowledge bit (ACK)

The Acknowledge bit is used to indicate a successful byte data transfer. The receiver sends a zero to acknowledge that

it has received each word (Device code, Slave address etc) from the transmitter.

SCL

SDA

tSU.STA

tHD.STA

tSU.STO

Start

condition

Stop

condition

SCL

SDA

tSU.DAT

tHD.DAT

tAA

tDH

1

89

SCL

(EEPROM input)

SDA

(Master output)

SDA

(EEPROM output)

Start

condition

Acknowledge

bit output