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CXA2061S Datasheet(PDF) 35 Page - Sony Corporation

Part No. CXA2061S
Description  Y/C/RGB/D for NTSC Color TVs
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Maker  SONY [Sony Corporation]
Homepage  http://www.sony.co.jp

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4. Signal processing
The CXA2061S is comprised of sync signal processing, H deflection signal processing, V deflection signal
processing, and Y/C/RGB signal processing blocks, all of which are controlled by the I2C bus.
1) Sync signal processing
The Y signal selected by the video switch is sync separated by the horizontal and vertical sync separation
The resulting horizontal sync separation signal and the H VCO output signal are phase compared, the AFC
loop is constructed, and an H pulse synchronized with the H sync is generated inside the IC. When the AFC is
locked to the H sync, 1 is output to the status register (H LOCK) and that can be used to detect the presence
of the video signal.
The vertical sync separation signal is sent to the V countdown block where the most appropriate window
processing is performed to obtain the V deflecticn timing. The AKB reference pulse and other V cycle timing
are generated from this V timing pulse.
The V retrace timing pulse and the sync separation signals are outputted from VTlM (Pin 5) according to the
VTIM SEL register setting.
2) H deflection signal processing
The H pulse obtained through sync processing is phase-compared with the H deflection pulse input from Pin 18
(HP/PROTECT) to control the phase of the H DRIVE output and the horizontal position of the picture on the
CRT. In addition, the compensation signal generated from the V sawtooth wave is superimposed, and the
vertical picture distortion is compensated.
The H deflection pulse is used to H blank the video signal. When the H deflection pulse has a narrow width,
the pulse generated by the IC can be added to the H deflection pulse and used as the H blanking pulse
Pin 18 is normally pulse input, but if the pin voltage drops to near the GND Ievel. H DRIVE output stops and 1
is outputted to the status register (H NG). To release this status, turn the power off and then on again.
3) V deflection signal processing
The V sawtooth wave is generated at the cycle of the V timing pulse output from the countdown system. After
performing wide deflection processing for this sawtooth wave, picture distortion adjustment is performed by the
V DRIVE and EW DRIVE function circuits and the signal is output as the V DRIVE and EW DRIVE signals.
4) Y signal processing
The Y/CVBS signal selected by the video switch is sent to the Y signal processing circuit.
The Y signal passes through the trap filter for eliminating the chroma signal, the delay line, the sharpness
control, the clamp and the black expansion circuits, and then is sent to the RGB signal processing circuit. The Y
signal processing circuit output can also be monitored at Pin 32 (R2 IN) by setting C DECOD register to 1. (In
this case, connect Pin 32 to Vcc via a 10k
Ω Ioad resistor.)
The differential waveform of the Y signal, delay for ubout 270ns from Y input is output from Pin 15 as VM OUT.
Set register C TRAP OFF to 0 (trap filter ON) when the CVBS signal is selected, or to 1 (trap filter OFF) when
the Y/C separated Y signal is selected.
The f0 of the internal filter is automatically adjusted within the IC.

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