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CAT25040VP2I.GT3 Datasheet(PDF) 8 Page - ON Semiconductor |
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CAT25040VP2I.GT3 Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 18 page CAT25010, CAT25020, CAT25040 http://onsemi.com 8 Write Status Register The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2 and 3 can be written using the WRSR command. Write Protection When WP input is low all write operations to the memory array and Status Register are inhibited. WP going low while CS is still low will interrupt a write operation. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the Status Register or memory array. The WP input timing is shown in Figure 8. Figure 7. WRSR Timing 01 2 3 4 5 6 7 8 10 911 12 13 14 SCK SI MSB HIGH IMPEDANCE DATA IN 15 SO 7 6 5 4 3 2 10 00 0 0 0 0 0 1 OPCODE Dashed Line = mode (1, 1) CS Figure 8. WP Timing SCK WP Dashed Line = mode (1, 1) WP CS tWPH tWPS |
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