SN65LBC180Q1

LOW POWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIR

SGLS251A − JULY 2004 − REVISED JUNE 2008

5

POST OFFICE BOX 655303

DRIVER SECTION

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIK

Input clamp voltage

II = − 18 mA

− 1.5

V

| VOD |

Differential output voltage magnitude

RL = 54 Ω,

See Figure 1

1.1

2.5

5

V

| VOD |

Differential output voltage magnitude

(see Note 3)

RL = 60 Ω,

See Figure 2

1.1

2

5

V

∆| VOD |

Change in magnitude of differential output

voltage (see Note 4)

See Figures 1 and 2

±0.2

V

VOC

Common-mode output voltage

1

2.5

3

V

∆| VOC |

Change in magnitude of common-mode output

voltage (see Note 4)

RL = 54 Ω,

See Figure 1

±0.2

V

IO

Output current with power off

VCC = 0,

VO = − 7 V to 12 V

±100

µA

IOZ

High-impedance-state output current

VO = − 7 V to 12 V

±100

µA

IIH

High-level input current

VI = 2.4 V

− 100

µA

IIL

Low-level input current

VI = 0.4 V

− 100

µA

IOS

Short-circuit output current

− 7 V

≤ VO ≤ 12 V

±250

mA

ICC

Supply current

Receiver disabled

Outputs enabled

5

mA

ICC

Supply current

Receiver disabled

Outputs disabled

3

mA

† All typical values are at VCC = 5 V and TA = 25°C.

NOTES:

3. The minimum VOD specification of the SN65LBC180 may not fully comply with ANSI RS-485 at operating temperatures below 0°C.

System designers should take the possibly lower output signal into account in determining the maximum signal-transmission

distance.

4.

∆|VOD| and ∆|VOC| are the changes in the steady-state magnitude of VOD and VOC, respectively, that occur when the input is

changed from a high level to a low level.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td(OD)

Differential output delay time

RL = 54 Ω

See Figure 3

7

12

18

ns

tt(OD)

Differential output transition time

RL = 54 Ω,

See Figure 3

5

10

20

ns

tPZH

Output enable time to high level

RL = 110 Ω,

See Figure 4

35

ns

tPZL

Output enable time to low level

RL = 110 Ω,

See Figure 5

35

ns

tPHZ

Output disable time from high level

RL = 110 Ω,

See Figure 4

50

ns

tPLZ

Output disable time from low level

RL = 110 Ω,

See Figure 5

35

ns