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SN64BCT657DW Datasheet(PDF) 1 Page - Texas Instruments

Part # SN64BCT657DW
Description  OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN64BCT657DW Datasheet(HTML) 1 Page - Texas Instruments

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T/R
A1
A2
A3
A4
A5
VCC
A6
A7
A8
ODD/EVEN
ERR
OE
B1
B2
B3
B4
GND
GND
B5
B6
B7
B8
PARITY
DW OR NT PACKAGE
(TOP VIEW)
SN64BCT657
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
AND 3STATE OUTPUTS
SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994
Copyright
1994, Texas Instruments Incorporated
3−1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
High-Impedance State During Power Up
and Power Down
3-State B Outputs Sink 64 mA and Source
15 mA
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
The SN64BCT657 contains eight noninverting buffers with parity generator/checker circuits and control signals.
The transmit/receive (T/R) input determines the direction of data flow. When T/R is high, data flows from the
A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode).
When the output-enable (OE) input is high, both the A and B ports are in the high-impedance state.
Odd or even parity is selected by a logic high or low level on the ODD/EVEN input. PARITY carries the parity
bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity
generator/checker in the receive mode.
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic
level that maintains the parity sense selected by the level at the ODD/EVEN input. For example, if ODD/EVEN
is low (even parity selected) and there are five high bits on the A bus, then PARITY is set to the logic high level
so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if
ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, then ERR
is low, indicating a parity error.
The SN64BCT657 is characterized for operation from − 40
°C to 85°C and 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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