G

G

1A

1B

2A

2B

3A

3B

4A

4B

4

12

2

1

6

7

10

9

14

15

3

5

11

13

1Y

2Y

3Y

4Y

SN55LVDS32 logic diagram

(positive logic)

SN55LVDS32-SP

SLLSEB4 – MARCH 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERABLE PART NUMBER

TOP-SIDE MARKING

CDIP - J

5962-9762201VEA

5962-9762201VEA

–55°C to 125°C

CFP - W

5962-9762201VFA

5962-9762201VFA

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

xxx

2

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Copyright © 2012, Texas Instruments Incorporated

Product Folder Link(s): SN55LVDS32-SP