SN54LS222A datasheet(3/12 Pages) TI1

Part #	SN54LS222A

Description	16 횞 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS

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SN54LS222A

16

× 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

WITH 3-STATE OUTPUTS

SDLS959A – DECEMBER 2001 – REVISED APRIL 2003

3

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

logic diagram (positive logic)

1

11

4

2

19

18

5

7

8

9

3

17

16

14

13

12

OE

CLR

LDCK

IRE

UNCK

ORE

D0

D1

D2

D3

IR

OR

Q0

Q1

Q2

Q3

16

Ring

Counter

CTR

DIV 16

Write

Address

Ring

Counter

CTR

DIV 16

Read

Address

COMP

RAM

16

× 4

+

CT = 1

+

CT = 1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

P

Q

1A

2A

C5

1

16

EN

≥1

1A,5D 2A

1

16

S

1D

C1

S

2D

C2

R

3D

C3

R

4D

C4

Q=P+1

P=Q+1

P=Q

EMPTY

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