DW OR NT PACKAGE

(TOP VIEW)

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OEA

A1

A2

A3

A4

A5

A6

A7

A8

ERR

CLR

GND

B1

B2

B3

B4

B5

B6

B7

B8

PARITY

OEB

CLK

SN74BCT29833

8BIT TO 9BIT PARITY BUS TRANSCEIVER

SCBS003C − SEPTEMBER 1987 − REVISED NOVEMBER 1993

Copyright

2−1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Outputs

Opposite Side From Outputs)

and AMD Am29833

Generator / Checker

Output

Parity-Error Flag

Small-Outline (DW) Packages and Standard

Plastic 300-mil DIPs (NT)

description

The SN74BCT29833 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between

data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted

from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not

an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device

so that the buses are effectively isolated.

A 9-bit parity generator/ checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports

with an open-collector parity-error (ERR) flag. ERR is clocked into the register on the rising edge of the CLK

input. The error flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are

low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced

error condition which gives the designer more system diagnostic capability. The SN74BCT29833 provides true

logic.

The SN74BCT29833 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUT AND I/O

OEB

OEA

CLR

CLK

Ai

∑ of H’s

Bi†

∑ of H’s

A

B

PARITY

ERR‡

FUNCTION

L

H

X

X

Odd

Even

NA

NA

A

L

H

NA

A data to B bus and generate parity

H

L

H

↑

NA

Odd

Even

B

NA

NA

H

L

B data to A bus and check parity

X

X

L

X

X

X

X

NA

NA

H

Clear error-flag register

H

H

H

L

H

H

No

↑

No

↑

↑

↑

X

X

Odd

Even

X

Z

Z

Z

NC

H

H

L

Isolation§

L

L

X

X

Odd

Even

NA

NA

A

H

L

NA

A data to B bus and generate inverted

parity

NA = not applicable, NC = no change, X = don’t care

† Summation of high-level inputs includes PARITY along with Bi inputs.

‡ Output states shown assume the ERR output was previously high.

§ In this mode, the ERR output, when enabled, shows inverted parity of the A bus.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.