Publication Number S70FL256P_00

Revision 04

Issue Date June 24, 2011

Distinctive Characteristics

Architectural Advantages

 Single power supply operation

– Full voltage range: 2.7 to 3.6V read and write operations

 Memory architecture

– Uniform 64 kB sectors

– Top or bottom parameter block (Two 64-kB sectors broken down

into sixteen 4-kB sub-sectors each) for each Flash die

– Uniform 256 kB sectors (no 4-kB sub-sectors)

– 256-byte page size

 Program

– Page Program (up to 256 bytes) in 1.5 ms (typical)

– Program operations are on a page by page basis

– Accelerated programming mode via 9V W#/ACC pin

– Quad Page Programming

 Erase

– Bulk erase function for each Flash die

– Sector erase (SE) command (D8h) for 64 kB and 256 kB sectors

– Sub-sector erase (P4E) command (20h) for 4 kB sectors

(for uniform 64-kB sector device only)

– Sub-sector erase (P8E) command (40h) for 8 kB sectors

(for uniform 64-kB sector device only)

 Cycling endurance

– 100,000 cycles per sector typical

 Data retention

– 20 years typical

 Device ID

– JEDEC standard two-byte electronic signature

– RES command one-byte electronic signature for backward

compatibility

 One time programmable (OTP) area on each Flash die for

permanent, secure identification; can be programmed and

locked at the factory or by the customer

 CFI (Common Flash Interface) compliant: allows host system

to identify and accommodate multiple flash devices

 Process technology

 Package option

– Industry Standard Pinouts

– 16-pin SO package (300 mils)

– 24-ball BGA (6 x 8 mm) package, 5 x 5 pin configuration

Performance Characteristics

 Speed

– Normal READ (Serial): 40 MHz clock rate

– FAST_READ (Serial): 104 MHz clock rate (maximum)

– DUAL I/O FAST_READ: 80 MHz clock rate or

20 MB/s effective data rate

– QUAD I/O FAST_READ: 80 MHz clock rate or

40 MB/s effective data rate

 Power saving standby mode

– Standby Mode 160 µA (typical)

– Deep Power-Down Mode 6 µA (typical)

Memory Protection Features

 Memory protection

– W#/ACC pin works in conjunction with Status Register Bits to

protect specified memory areas

– Status Register Block Protection bits (BP2, BP1, BP0) in status

General Description

This document contains information for the S70FL256P device, which is a dual die stack of two S25FL129P die. For detailed

specifications, please refer to the discrete die data sheet:

S70FL256P

256-Mbit CMOS 3.0 Volt Flash Memory

with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus

Data Sheet

Document

Publication Identification Number (PID)

S25FL129P Data Sheet

S25FL129P_00