ThunderLAN

™ TNETE110A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996

10

POST OFFICE BOX 1443

10 Base-T physical layer (continued)

TNETE110A

PCI

FXMTP

FXMTN

FRCVP

FRCVN

RJ-45

Figure 2. Schematic for 10 Base-T Network Interface Using TNETE110A

FIFO pointer registers (FPREGS)

The FPREGS are used to implement circular buffer FIFOs in the SRAM. They are a collection of pointer and

counter registers used to maintain the FIFO operation. Both the PCIIF and PH use FPREGS to determine where

to read or write data in the SRAM and to determine how much data the FIFO contains.

FIFO SRAM (FSRAM)

The FSRAM is a conventional SRAM array accessed synchronously to the PCI bus clock. Access to the RAM

is allocated on a time-division multiplexed (TDM) basis, rather than through a conventional shared bus. This

removes the need for bus arbitration and provides ensured bandwidth. Half of the RAM accesses (every other

cycle) are allocated to the PCI controller. It has a 64-bit access port to the RAM, giving it 1 Gbps of bandwidth,

sufficient to support 32-bit data streaming on the PCI bus. The PH has one quarter of the RAM accesses, and

its port may be up to 64 bits wide. A 64-bit port for the PH provides 512 Mbps of bandwidth, more than sufficient

for a full-duplex 100-Mbps network. The remaining RAM accesses can be allocated toward providing even more

PH bandwidth. The RAM also is accessible (for diagnostic purposes) from the TNETE110A internal data bus.

Host DIO (mapped I / O) accesses are used by the host to access internal TNETE110A registers and for adapter

test.

Some of the features of the FSRAM follow:

Supporting 1.5K byte of FIFO per channel allows full-frame buffering of Ethernet frames.

test-access port (TAP)

Compliant with IEEE Standard 1149.1, the TAP is composed of five pins that are used to interface serially with

the device and the board on which it is installed for boundary-scan testing.