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TNETE100PM Datasheet(PDF) 8 Page - Texas Instruments |
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TNETE100PM Datasheet(HTML) 8 Page - Texas Instruments |
8 / 27 page ThunderLAN ™ TNETE100PM PCI ETHERNET ™ CONTROLLER WITH POWER MANAGEMENT SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN SPWS026 – OCTOBER 1996 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions (Continued) PIN TYPE† DESCRIPTION NAME NO. TYPE† DESCRIPTION MEDIA-INDEPENDENT INTERFACE (100-Mbps CSMA / CD AND DEMAND PRIORITY) (CONTINUED) MCRS 81 I Carrier sense. MCRS indicates a frame-carrier signal is being received. MDCLK 91 O Management data clock. MDCLK is part of the serial management interface to physical-media independent (PMI) / PHY chip. MDIO 93 I/O Management data I / O. MDIO is part of the serial management interface to PMI / PHY chip. MRCLK 82 I Receive clock. MRCLK is the receive clock source from the attached PHY and PMI device. MRST 95 O MII reset. MRST is the reset signal to the PMI / PHY front-end (active low). MRXD0 MRXD1 MRXD2 MRXD3 83 85 86 87 I Receive data. MRXD[3 : 0] is the nibble-receive data from the physical-media dependent (PMD) front end. In demand-priority mode, ThunderLAN reads the frame priority of incoming frames on these pins on the cycle before assertion of MRXDV (the cycle before frame reception begins). • MRXD1 indicates the transmission priority of the received frame. A value of zero indicates normal transmission, and a value of one indicates priority transmission. Data on these pins is always synchronous to MRCLK. MRXDV 89 I Receive data valid. MRXDV indicates data on MRXD[3 : 0] is valid. MRXER 90 I Receive error. MRXER indicates reception of a coding error on received data. MTCLK 71 I Transmit clock. MTCLK is the transmit clock source from the attached PHY and PMI device. MTXD0 MTXD1 MTXD2 MTXD3 72 73 74 76 O Transmit data. MTXD[3 : 0] is the nibble-transmit data from TNETE100PM. When MTXEN is asserted, these pins carry transmit data. In demand-priority mode, the TNETE100PM drives the request state of the controller on these pins when MTXEN is not asserted (frame transmission not in progress). • MTXD0 asserted indicates the TNETE100PM is requesting frame transmission. • MTXD1 indicates the transmission priority required. A value of zero indicates normal transmission, and a value of one indicates high-priority transmission. Data on these pins is always synchronous to MTCLK. MTXER 78 O Transmit error. MTXER allows coding errors to be propagated across the MII. MTXEN 77 O Transmit enable. MTXEN indicates valid transmit data on MTXD[3 : 0]. NETWORK INTERFACE (10 Base-T AND AUI) ACOLN ACOLP 111 109 A AUI-receive pair. ACOLN and ACOLP are differential line receiver inputs and connect to receive pair through transformer isolation, etc. ARCVN ARCVP 108 106 A AUI-receive pair. ARCVN and ARCVP are differential line receiver inputs and connect to receive pair through transformer isolation, etc. AXMTP AXMTN 99 100 A AUI-transmit pair. AXMTP and AXMTN are differential line-transmitter outputs. FATEST 118 A Analog test pin. FATEST provides access to the filter of the reference PLL. This pin must be left as a “no connect”. FIREF 116 A Current reference. FIREF is used to set a current reference for the analog circuitry. FONLY 120 A Front-end only pin. The FONLY pin should be tied low for systems not requiring the power management capabilites of the TNETE100PM. FRCVN FRCVP 105 103 A 10 Base-T receive pair. FRCVN and FRCVP are differential line-receiver inputs and connect to receive pair through transformer isolation, etc. FXTL1 FXTL2 113 114 A Crystal oscillator pins. FXTL1 is driven from a 20-MHz crystal oscillator module. FXMTP FXMTN 97 98 A 10 Base-T transmit pair. FXMTP and FXMTN are differential line-transmitter outputs. † I = input, O = output, A = Analog NOTE 1: This pin should be tied to VDD with a 4.7-kW – 10-kW pullup resistor. |
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