TNETA1500

155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

SDNS021D – MARCH 1994 – REVISED JANUARY 1998

8

POST OFFICE BOX 655303

receive operation (continued)

The location of the J1 byte in the SPE is determined from the H1 and H2 bytes in the transport overhead. The

location of the J1 byte does not change from the previous frame unless the first four bits of H1 are set to 1001

(the new-data flag) or the pointer value contained in H1 and H2 is different for three consecutive frames. The

location of J1 also can be incremented or decremented by a 1-byte position by inverting certain bits in the H1

and H2 byte pointer. If bits 7, 9, 11, 13, and 15 are inverted, the location of J1 is incremented one time slot. If

bits 8, 10, 12, 14, and 16 are inverted, the location of J1 is decremented one time slot. Subsequent pointers

contain the new offset.

The TNETA1500 provides a loss-of-pointer (LOP) alarm to indicate that either an invalid pointer was detected

in the incoming H1 and H2 bytes or a new-data flag NDF (set to a value of 1001 – the first four bits of H1) was

found in eight consecutive frames. The LOP alarm goes inactive when a valid pointer with the NDF set to 0110

is detected in three consecutive frames. The device also provides a path-AIS alarm to indicate that a path-AIS

condition has been detected in the H1 and H2 bytes. A path-AIS condition is detected as an all-1s condition in

bytes H1 and H2 for three consecutive frames. The path-AIS alarm goes inactive when a valid pointer, with the

NDF set to 0110, is detected for three consecutive frames. The LOP alarm is not set if a path-AIS condition is

detected. The LOP alarm is indicated by an external signal and by the interrupt register. The path-AIS alarm

is indicated only by the interrupt register.

The B3 BIP-8 byte is calculated over the contents of the STS-3c SPE, which begins with the J1 byte. The value

calculated for B3 is compared with the value found in the next frame. If a B3 parity error occurs, the B3

parity-error bit is set in the interrupt register and INTR goes active low to notify the controller.

The TNETA1500 monitors the receive G1 byte for a path far-end receive failure (path FERF) and path

remote-defect indication (path RDI) alarms. A path FERF occurs when bits 1–4 of the G1 byte are set to a value

of 1001. The path FERF alarm goes inactive when bits 1–4 of the G1 byte are set to a non-1001 value. A path

RDI occurs when bit 5 of the G1 byte is set to a value of 1 for ten consecutive frames. The path RDI alarm goes

inactive when bit 5 of the G1 byte is set to a value of 0 for ten consecutive frames. Both the path FERF and path

RDI alarms are indicated through interrupt register 3.

Once the STS-3c SPE is located, the ATM cells are identified and extracted. Cell delineation is accomplished

by computing the header-error check (HEC) for the first four bytes after the J1 byte and comparing the calculated

value with the fifth byte. If the values do not match, the process advances one byte and then repeats. This

process continues until a match between the calculated value and the fifth byte occurs. Cell alignment is

assumed to have occurred when seven consecutive matches occur. Until cell alignment occurs, the

loss-of-cell-alignment (LOCA) alarm remains active. Once cell alignment is established, it is monitored

constantly for a LOCA condition. A LOCA condition is declared (LOCA goes active) when seven consecutive

cells occur with header errors. At this point, the hunting process starts over.

The receive side detects multiple-bit errors and corrects single-bit errors occurring in the 5-byte ATM header

of incoming ATM cells by using the HEC byte. This feature is deactivated by setting a bit in control register 1

(see Table 6). The ATM cells with multiple-bit header errors are dropped, unless a bit is set in control register 1

(see Table 6) to disable the dropping of cells with uncorrectable errors. An 8-bit saturating counter (accessible

through the controller interface) counts the number of ATM cells with multiple-bit ATM-header errors.

After the ATM cells are extracted, they are descrambled. The 48-byte payload in the ATM cell is scrambled at

so that it can be sent to the next device.

The TNETA1500 has the capability of dropping idle and unassigned cells from the receive-data stream. An idle

cell is defined as a cell with a 5-byte ATM header set to a value of 00 00 00 01 52 (hex) and an unassigned cell

is defined as a cell with a 5-byte header of 00 00 00 00 55 (hex). In both cases, the payload is ignored. The

dropping of idle and/or unassigned cells can be disabled through control register 1 (CR1) in the controller

interface.