TMS417800A

2097152 BY 8-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMKS888B – AUGUST 1996 – REVISED SEPTEMBER 1997

10

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

RAS

CAS

Address

W

OE

DQ0 – DQ7

tRC

Row

Column

Don’t Care

Don’t Care

Don’t Care

Don’t Care

Don’t Care

Valid Data Out

tRAS

tRP

tCSH

tT

tRCD

tRSH

tCRP

tCAS

tRAD

tASC

tRAL

tASR

tRCS

tCAH

tRRH

tRCH

tCAC

tOFF

tAA

tCLZ

tRAC

tOEA

tROH

tOEZ

tCP

See Note A

Hi-Z

tRAH

tCAL

tOH

tOHO

NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.

Figure 2. Read-Cycle Timing