TM4TT64KPN 4194304 BY 64BIT

TM8TT64KPN 8388608 BY 64BIT

SYNCHRONOUS DYNAMIC RAM MODULES

SMMS699A − MARCH 1998 − REVISED AUGUST 1998

8

POST OFFICE BOX 1443

’xTT64KPN-8

’xTT64KPN-8A

UNIT

MIN

MAX

MIN

MAX

UNIT

tCK2

Cycle time, CK

CAS latency = 2

10

15

ns

tCK3

Cycle time, CK

CAS latency = 3

8

8

ns

tCH

Pulse duration, CK high

3

3

ns

tCL

Pulse duraction, CK low

3

3

ns

tAC2

Access time, CK high to data out

(see Note 11)

CAS latency = 2

6

7.5

ns

tAC3

Access time, CK high to data out

(see Note 11)

CAS latency = 3

6

6

ns

tOH

Hold time, CK high to data out

3

3

ns

tLZ

Delay time, CK high to DQ in low-impedance state

(see Note 12)

1

1

ns

tHZ

Delay time, CK high to DQ in high-impedance state

(see Note 13)

8

8

ns

tIS

Setup time, address, control, and data input

2

2

ns

tIH

Hold time, address, control, and data input

1

1

ns

tIH

Hold time, address, control, and data input

1

1

ns

tCESP Power down/self-refresh exit time

10

10

ns

tRAS

Delay time, ACTV command to DEAC or DCAB command

48

100 000

48

100 000

ns

tRC

Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command

68

68

ns

tRCD

Delay time ACTV command to READ, READ-P, WRT, or WRT-P command

(see Note 14)

20

20

ns

tRP

Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command

20

20

ns

tRRD

Delay time, ACTV command in one bank to ACTV command in the other bank

16

16

ns

tRSA

Delay time, MRS command to ACTV, MRS, REFR, or SLFR command

16

16

ns

tAPR

Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command

tRP −(CL−1)*tCK

ns

tAPW

Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command

tRP + 1 tCK

ns

tT

Transition time

1

5

1

5

ms

† All references are made to the rising transition of CK unless otherwise noted.

‡ Specifications in this table represent a single SDRAM device.

NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced

from the rising transition of ck that is read latency (one cycle after the READ command). Access time is measured at output reference

level 1.4 V.

12. tLZ is measured from the rising transition of ck that is read latency (one cycle after the READ command).

13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.

14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.