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UCD7231RTJR Datasheet(PDF) 6 Page - Texas Instruments

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Part # UCD7231RTJR
Description  Digital Control Compatible Synchronous-Buck Gate Driver With Current Sense and Fault Protection
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

UCD7231RTJR Datasheet(HTML) 6 Page - Texas Instruments

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UCD7231
SLUS997 – NOVEMBER 2009 – REVISED JANUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, 4.7 µF from VGG to PGND, 1.0 µF from BP3 to AGND, 0.22 µF from BST to SW, TA = TJ = –40°C to +125°C,
RDLY = 8.06k
Ω, SRE Mode = 3.3V, VGG DIS tied to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE BLANKING (RDLY, HS Sense)
IRDLY
RDLY source current
8.06 k
Ω resistor from RDLY to AGND
80
90
100
µA
RDLY resistance range
7.5
8.06
10
k
Ω
RDLY = 8.06 k
Ω. From SW rising to HS fault comparator
tBLANK
HS blanking time
80
100
120
ns
enabled
IHS Sense
HS Sense sink current
RHS Sense = 2.0 kΩ to VIN, VIN = 12 V
100
µA
HS fault detection time. Delay after tBLANK
RDLY = 8.06 k
Ω, RHS Sense = 2.0 kΩ to VIN, VIN = 12 V,
tHSFAULT_HS
20
ns
until HS Gate falling
VIN – VSW = 220 mV
HS fault detection time. Delay after tBLANK
RDLY = 8.06 k
Ω, RHS Sense = 2.0 kΩ to VIN, VIN = 12 V,
tHSFAULT_LS
30
ns
until LS Gate falling
VIN – VSW = 220 mV
CURRENT SENSE AMPLIFER (IMON, CSP, CSN)
V(IMON) at no load
CSP = CSN = 1.8 V
0.490
0.500
0.510
V
Closed loop DC gain
CSP – CSN = 10 mV; 0.5 V
≤ CSN ≤ 3.3 V
48.5
50
51.5
V/V
Gain with 2.49k resistors in series with CSP, CSN
45.3
47.6
49.6
V/V
Input impedance
Differential, CSP – CSN
100
k
Ω
VCM
Input common mode voltage range
VCM(max) is limited to (VGG – 1.2 V)
–0.3
5.6
V
V(IMON)MIN
CSP = 1.2 V; CSN = 1.3 V; I(IMON) = –250 µA
0.1
0.15
V
V(IMON)MAX
CSP = 1.3 V; CSN = 1.2 V; I(IMON) = 500 µA
3
3.2
3.3
V
Sampling Rate
5
Msps
LOW-SIDE OUTPUT DRIVER (LS Gate)
Peak Source Current(1)
VGG = 6.2 V, PWM = Low, LS Gate = 3 V
6
A
Peak Sink Current (1)
VGG = 6.2 V, PWM = High, LS Gate = 3 V
6
A
tRL
Rise Time
CL = 6 nF, VIN = 12 V, VGG = 6.2 V
30
ns
tFL
Fall Time
CL = 6 nF, VIN = 12 V, VGG = 6.2 V
20
ns
Output with VGG <UVLO
VGG = 1.0 V, Isink = 10 mA
0
0.5
V
Propagation Delay from PWM to LS Gate
CL = 3 nF, PWM falling SW = 0 V, VGG = 6.2 V
46
ns
HIGH-SIDE OUTPUT DRIVER (HS Gate)
VIN = 12 V, BST = 6.2 V, PWM = High,
Source current(1)
4
A
HS Gate = 3 V
VIN = 12 V, BST = 6.2 V, PWM = Low,
Sink current(1)
4
A
HS Gate = 3 V
tRH
Rise time
CL = 3 nF HS Gate to SW, VGG = 6.2 V
27
ns
tFH
Fall time
CL = 3 nF HS Gate to SW, VGG = 6.2 V
21
ns
CL = 3 nF HS Gate to SW, PWM rising,
Propagation delay from PWM to HS Gate
50
ns
SW = 0 V, VGG = 6.2 V
SWITCHING TIME
tDLH
HS gate turn-off propagation delay
CL = 3 nF
16
ns
tDLL
LS gate turn-off propagation delay
CL = 3 nF
15
ns
tDTH
Dead time LS; Gate off to HS; Gate on
CL = 3 nF
12
ns
tDTL
Dead time HS; Gate off to LS; Gate on
CL = 3 nF
15
ns
BOOTSTRAP DIODE
VF
Forward voltage
Forward bias current 100 mA
0.4
V
THERMAL SHUTDOWN
Rising threshold(1)
155
165
175
°C
Falling threshold(1)
135
145
155
°C
Hysteresis
20
°C
(1)
As designed and characterized. Not 100% tested in production.
6
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Product Folder Link(s): UCD7231


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