18

17

1

2

16

13

4

6

CSBIAS

IO

IN

SRE

VDD

3V3

AGND

ILIM

UCD7230A

CS+

BST

14

12

15

11

SW

OUT1

PVDD OUT2

10

PGND

5

CLF

8

POS

9

NEG

7

AO

20

19

3

DLY

UDG-09163

+ 0.6 V

48 x

Drive and Deadtime Control Logic

(D, 1-D)

+

Current Limit

Logic

UVLO

3V3

Reg

+

Overcurrent

Blanking

Enable

I

DLY

ILIM/10

UCD7230A

SLUS995 – NOVEMBER 2009

www.ti.com

TERMINAL FUNCTIONS (continued)

NAME

No.

I/O

DESCRIPTION

Synchronous Rectifier Enable. The SRE pin is a high impedance digital input capable of accepting 3.3-V

SRE

19

I

logic level signals, used to disable the synchronous rectifier switch. The synchronous rectifier is disabled

when this signal is low. A Schmitt trigger input comparator desensitizes this pin from external noise.

SW

15

I/O

OUT1 gate drive return and square wave input to output inductor.

Supply input pin to power the internal circuitry except the driver outputs. The UCD7230A accepts an input

VDD

18

-

range of 4.5 V to 15.5 V.

FUNCTIONAL BLOCK DIAGRAM

8

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Product Folder Link(s): UCD7230A