1

OUT

VDD

IN

3

ENBL

7

VDD

8

INVERTING

NON

INVERTING

PGND

6

OUT

5

4

AGND

VDD

2

INVERTING

UCC37321

0

0

0

0

1

0

0

1

1

1

1

0

NON

INVERTING

UCC37322

0

0

0

0

1

0

0

0

1

1

1

1

ENBL

IN

OUT

INPUT/OUTPUT TABLE

RENBL

100 kΩ

UCC27321-Q1, UCC27322-Q1

SLUSA13C – FEBRUARY 2010 – REVISED MARCH 2012

www.ti.com

Using a design that inherently minimizes shoot-through current, the outputs of these devices can provide high

gate drive current where it is most needed at the Miller plateau region during the MOSFET switching transition. A

unique hybrid output stage paralleling bipolar and MOSFET transistors (TrueDrive) allows efficient current

delivery at low supply voltages. With this drive architecture, UCC37321/2 can be used in industry standard 6-A,

9-A and many 12-A driver applications. Latch-up and ESD protection circuits are also included. Finally, the

UCC37321/2 provides an enable (ENBL) function to have better control of the operation of the driver

applications. ENBL is implemented on pin 3, which was previously left unused in the industry-standard pinout. It

is internally pulled up to VDD for active-high logic and can be left open for standard operation.

In addition to SOIC-8 (D) package offerings, the UCC37321/2 also comes in the thermally enhanced but tiny 8-

pin MSOP PowerPAD (DGN) package. The PowerPAD package drastically lowers the thermal resistance to

extend the temperature operation range and improve the long-term reliability.

OUTPUT

ORDERABLE

TOP-SIDE

CONFIGURATION

PART NUMBER

MARKING

Inverting

SOIC – D

Reel of 2500

UCC27321QDRQ1

27321Q

–40°C to 125°C

SOIC – D

Reel of 2500

UCC27322QDRQ1

27322Q

Noninverting

PowerPAD – DGN

Reel of 2500

UCC27322QDGNRQ1

EACQ

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Table 1. TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Common ground for input stage. This ground should be connected very closely to the source of the power

AGND

4

—

MOSFET which the driver is driving. Grounds are separated to minimize ringing affects due to output

switching di/dt,l which can affect the input threshold.

Enable input for the driver with logic-compatible threshold and hysteresis. The driver output can be enabled

ENBL

3

I

and disabled with this pin. It is internally pulled up to VDD with a 100-k

Ω resistor for active-high operation.

The output state when the device is disabled is low, regardless of the input state.

IN

2

I

Input signal of the driver, which has logic-compatible threshold and hysteresis.

Driver outputs that must be connected together externally. The output stage is capable of providing 9-A peak

OUT

6, 7

O

drive current to the gate of a power MOSFET.

Common ground for output stage. This ground should be connected very closely to the source of the power

PGND

5

—

MOSFET which the driver is driving. Grounds are separated to minimize ringing affects due to output

switching di/dt, which can affect the input threshold.

Supply voltage and the power input connections for this device. These pins must be connected together

VDD

1, 8

I

externally.

2

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