HIGH CURRENT OUTPUTS

UDG-95114

GROUND PLANES

UC1825A-SP

Each totem pole output of the UC1825A can deliver a 2-A peak current into a capacitive load. The output can

slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC) and power ground

(PGND) pins help decouple the device's analog circuitry from the high-power gate drive noise. The use of 3-A

Schottky diodes (1N5120, USD245, or equivalent) as shown in the Figure 13 from each output to both VC and

PGND are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of

inductive/capacitive load, typical of a MOSFET gate. Schottky diodes must be used because a low forward

voltage drop is required. DO NOT USE standard silicon diodes.

Figure 12. Power MOSFET Drive Circuit

Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct

operation of the chip. A ground plane must be employed. A unique section of the ground plane must be

designated for high di/dt currents associated with the output stages. This point is the power ground to which the

PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a

single point, although this is not necessary if the high di/dt paths are well understood and accounted for. VCC

should be bypassed directly to power ground with a good high frequency capacitor. The sources of the power

MOSFET should connect to power ground as should the return connection for input power to the system and the

bulk input capacitor. The output should be clamped with a high current Schottky diode to both VCC and PGND.

Nothing else should be connected to power ground.

VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency

capacitor. Low ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog

circuitry should likewise be bypassed to the signal ground plane.

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