TPS84320

SLUSAH7

– SEPTEMBER 2011

www.ti.com

PIN DESCRIPTIONS

TERMINAL

DESCRIPTION

NAME

NO.

1

2

Zero VDC reference for the analog control circuitry. Connect AGND to PGND at a single point. Connect near

AGND

the output capacitors. See Figure 43 for a recommended layout.

34

45

8

Inhibit and UVLO adjust pin. Use an open drain or open collector output logic to control the INH function. A

INH/UVLO

resistor divider between this pin, AGND and VIN adjusts the UVLO voltage. Tie both pins together when

9

using this control.

3

4

5

15

16

18

Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These

DNC

19

pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.

20

22

23

30

31

32

36

Common ground connection for the PVIN, VIN, and VOUT power connections. See Figure 43 for a

PGND

37

recommended layout.

38

10

11

12

Phase switch node. These pins should be connected to a small copper island under the device for thermal

PH

13

relief. Do not place any external component on this pin or tie it to a pin of another function.

14

17

46

PWRGD

33

Power good fault pin. Asserts low if the output voltage is low. A pull-up resistor is required.

39

Input switching voltage. This pin supplies voltage to the power switches of the converter. See Figure 43 for a

PVIN

40

recommended layout.

41

This pin automatically selects between RT mode and CLK mode. An external timing resistor adjusts the

RT/CLK

35

switching frequency of the device. In CLK mode, the device synchronizes to an external clock.

Remote sense connection. Connect this pin to VOUT at the load for improved regulation. This pin must be

SENSE+

44

connected to VOUT at the load, or at the module pins.

Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time.

SS/TR

6

A voltage applied to this pin allows for tracking and sequencing control.

Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor with a SS

STSEL

7

interval of approximately 1.1 ms. Leave this pin open to enable the TR feature.

VADJ

43

Connecting a resistor between this pin and AGND sets the output voltage.

Input bias voltage pin. Supplies the control circuitry of the power converter. See Figure 43 for a

VIN

42

recommended layout.

6

Copyright

© 2011, Texas Instruments Incorporated