Datasheet

Datasheet

11/24

TSZ02201-0B2B0H300010-1-2

© 2012 ROHM Co., Ltd. All rights reserved.

12.Jul.2012 Rev.001

www.rohm.com

TSZ22111・15・001

BD91411GW

7-2-5.Shortening of second detection by Enumeration preparation

The second detection after primary is detected has already been shortened while judging the USB port when a portable

device equipped with this LSI is possible Enumeration and CDP will be detected compulsorily.

7-2-6.Sequence Retrying.

After the completion of the USB port detection (SDPDET, CDPDET, or DCPDET in the state transition diagram), detection can

be retried at any timing. Retries will not be accepted while USB port detection is operating.

7-2-7.Deactivation of USB port detection by External PIN and Internal Register.

The combination of the USBDISEN external pin and the USBDETCTRL@02h register makes it possible to freely turn on or off

the USB port detection function.

7-3.Signal paths

This LSI is capable of controlling the signal paths between the HDPR/HDML pins and the HDP1/HDM1,

HDP2/HDM2,EARR/EARL, and MICOUT pins from the I2C interface. It is capable of controlling the signal path between the

VB pin and the MICOUT pin as well.

For MHL transmission/USB transmission, use the path to HDP1/HDM1 or to HDP2/HDM2 enabling high-speed transmission.

The signal paths to EARR/EARL and to MICOUT do not support high-speed signal transmission.

7-3-1.HDPR/HDML Signal paths

The HDPR pin has a signal path to each of the HDP1, HDP2, EARR, and MICOUT pins, whereas the HDML pin has a signal

path to each of the HDM1, HDM2, and EARL pins.

7-3-2.Configuration of MUXSW initial path by DSS PIN.

The initially selected state of the signal paths can be controlled by the DSS pin. When the state of the DSS pin is "L," the signal

path to the HDP1/HDM1 pin will be selected. When the state of the DSS pin is "H," the signal path to the HDP2/HDM2 pin will

be selected.

7-3-3.Pull-down resistance in EARR/RARL pin.

A 500Ω pull-down resistance exists in the signal paths to the EARL pin and the EARR pin. The ON/OFF state of these

resistances can be controlled independently by the register.

7-3-4.Signal path between ID pin and CBUS pin.

The ID pin has a signal path to the CBUS pin. The signal paths can be selected in the register.

7-4.Interrupt report with INTB pin.

This LSI reports such events as the completion of detection of the resistor connected to the ID pin and the completion of USB

port detection to trigger as interrupt signals to the INTB pin. The INTB pin is of an Nch open drain structure, and the logic of

an interrupt to be triggered is determined by the register. In the initial state, the INTB pin is set to be driven to L when an

interrupt is triggered. The output of the pin is Hi-Z when there is no interrupt.

7-4-1.Active level selector of INTB.

The active level for interrupts can be selected in the register. In the initial state, the value in the register is "0," which drives the

INTB pin to "L" at the time of the trigger of an interrupt. By writing "1" into the register, the INTB pin will open (Hi-Z) at the time of

the trigger of an interrupt.

7-4-2.Interrupt polarity.

Interrupt polarity can be changed by writing register. In initial state INTB is droved with “L” when interrupt will be triggered.

7-5.Detection of Cradle and VBUS by VBDET pin and VCDET pin.

The application of a voltage from the VBUS or cradle can be detected using the VBDET pin or VCDET pin.

7-6.Detection of Cradle and VBUS by I2C interface reading.

The application of the voltage to the VBUS pin or cradle can be checked through the I2C interface by controlling of registers.

7-7.Detection of Over current state by I2C Interface reading.

This LSI has an independent OCP in each of the VB and VC power supply systems, and its over-current state can be

detected by accessing it from the I2C interface.

7-8.Thermal Shut down.

If the junction temperature exceeds the set temperature, the thermal shutdown circuit will become activated and turn off the

SW1 and SW2 of the OVP. The TSD detection temperature is 180℃, and the hysteresis temperature for recovery is 10℃.

7-9.VBREG Regulator.

This LSI has a regulator driven by the VBUS voltage. The output from the regulator can be turned on by the VBREG pin in the

default state by increasing the voltage of the VB pin to UVLO or a higher level. The VBREG output pin is available for external

applications, and two output voltage levels can be selected by LDOSEL pin.