6

C6(nF)

V b

1.1

C6(nF)

0.765

1.1

Tss(ms) =

=

Iss( A)

´

´

´

´

f

m

TPS54427

www.ti.com

SLVSB43

– NOVEMBER 2011

OVERVIEW

The TPS54427 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It

operates using D-CAP2

™ mode control. The fast transient response of D-CAP2™ control reduces the output

capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low

ESR output capacitors including ceramic and special polymer types.

DETAILED DESCRIPTION

PWM Operation

The main control loop of the TPS54427 is an adaptive on-time pulse width modulation (PWM) controller that

supports a proprietary D-CAP2

™ mode control. D-CAP2™ mode control combines constant on-time control with

an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with

both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one

shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to

maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The

one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the

reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need

for ESR induced output ripple from D-CAP2

™ mode control.

PWM Frequency and Adaptive On-Time Control

TPS54427 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The

TPS54427 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to

set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the

output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN pin becomes high, 6-uA current begins charging the capacitor

which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.

The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is

6-

µA.

(1)

The TPS54427 contains a unique circuit to prevent current from being pulled from the output during startup if the

output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start

becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting

the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a

cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.

This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and

ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to

normal mode operation.

Current Protection

The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The

switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This

voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature

compensated.

During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,

Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current

monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.

If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented

per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the

voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching

Copyright

© 2011, Texas Instruments Incorporated

Submit Documentation Feedback

7

Product Folder Link(s) :TPS54427