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SST36VF1601-70-4C-EK Datasheet(PDF) 3 Page - Silicon Storage Technology, Inc |
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SST36VF1601-70-4C-EK Datasheet(HTML) 3 Page - Silicon Storage Technology, Inc |
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3 / 26 page  Data Sheet 16 Mbit Concurrent SuperFlash SST36VF1601 3 ©2001 Silicon Storage Technology, Inc. S71142-06-000 11/01 373 The Chip-Erase operation is initiated by executing a six- byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid Read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing dia- gram, and Figure 22 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Write Operation Status Detection The SST36VF1601 provides one hardware and two soft- ware means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The hardware detection uses the Ready/Busy# (RY/ BY#) output pin. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of- Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase opera- tion. The actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a Ready/Busy# (RY/ BY#), a Data# Polling (DQ7) or Toggle Bit (DQ6) read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an errone- ous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has com- pleted the Write cycle, otherwise the rejection is valid. Ready/Busy# (RY/BY#) The SST36VF1601 includes a Ready/Busy# (RY/BY#) output signal. RY/BY# is actively pulled low while during an internal Erase or Program operation is in progress. RY/BY# is an open drain output that allows several devices to be tied in parallel to VDD via an external pull up resistor. RY/ BY# is high impedance whenever CE# is high or RST# is low. There is a 1 µs bus recovery time (TBR) required before valid data can be read on the data bus. New commands can be entered immediately after RY/BY# goes high. Data# Polling (DQ7) When the SST36VF1601 is in the internal Program opera- tion, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. During internal Erase opera- tion, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling (DQ7) timing diagram and Figure 20 for a flowchart. There is a 1 µs bus recovery time (TBR) required before valid data can be read on the data bus. New com- mands can be entered immediately after DQ7 becomes true data. Toggle Bit (DQ6) During the internal Program or Erase operation, any con- secutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sec- tor-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 20 for a flowchart. There is a 1 µs bus recovery time (TBR) required before valid data can be read on the data bus. New commands can be entered immediately after DQ6 no longer toggles. Data Protection The SST36VF1601 provides both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvert- ent writes during power-up or power-down. Hardware Block Protection The SST36VF1601 provides a hardware block protection which protects the outermost 4 KWord in the larger bank. The block is protected when WP# is held low. See Figure 1 for Block-Protection location. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed. |
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