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SST32HF401-70-4C-L3K Datasheet(PDF) 2 Page - Silicon Storage Technology, Inc |
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SST32HF401-70-4C-L3K Datasheet(HTML) 2 Page - Silicon Storage Technology, Inc |
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2 / 26 page  2 Preliminary Specifications Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402 ©2001 Silicon Storage Technology, Inc. S71209-00-000 9/01 557 consumption, when compared with multiple chip solutions. The SST32HF20x/40x inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to pro- gram and has a shorter erase time, the total energy con- sumed during any Erase or Program operation is less than alternative flash technologies. The SuperFlash technology provides fixed Erase and Pro- gram times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. Device Operation The ComboMemory uses BES# and BEF# to control oper- ation of either the SRAM or the flash memory bank. When BES# is low, the SRAM Bank is activated for Read and Write operation. When BEF# is low the flash bank is acti- vated for Read, Program or Erase operation. BES# and BEF# cannot be at low level at the same time. If BES# and BEF# are both asserted to low level bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by SRAM Bank and flash bank which minimizes power consumption and loading. The device goes into standby when both bank enables are high. SRAM Operation With BES# low and BEF# high, the SST32HF201/401 operate as 64K x16 CMOS SRAM, and the SST32HF202/ 402 operates as 128K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SST32HF201/401 SRAM is mapped into the first 64 KWord address space of the device, and the SST32HF202/402 SRAM is mapped into the first 128 KWord address space. When BES# and BEF# are high, both memory banks are deselected and the device enters standby mode. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 3 for SRAM read and write data byte control modes of operation. SRAM Read The SRAM Read operation of the SST32HF20x/40x is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data from the outputs. BES# is used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 2 for the Read cycle timing diagram. SRAM Write The SRAM Write operation of the SST32HF20x/40x is controlled by WE# and BES#, both have to be low for the system to write to the SRAM. During the Word-Write oper- ation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The write time is measured from the last falling edge to the first rising edge of BES# or WE#. See Figures 3 and 4 for the Write cycle timing diagrams. Flash Operation With BEF# active, the SST32HF201/202 operate as 128K x16 flash memory and the SST32HF401/402 operates as 256K x16 flash memory. The flash memory bank is read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and during the internally timed Erase and Program operations. Flash Read The Read operation of the SST32HF20x/40x devices is controlled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are deselected and only standby power is consumed. OE# is the output con- trol and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to Figure 5 for further details. Flash Erase/Program Operation SDP commands are used to initiate the flash memory bank Program and Erase operations of the SST32HF20x/40x. SDP commands are loaded to the flash memory bank using standard microprocessor write sequences. A com- mand is loaded by asserting WE# low while keeping BEF# low and OE# high. The address is latched on the falling edge of WE# or BEF#, whichever occurs last. The data is latched on the rising edge of WE# or BEF#, whichever occurs first. Flash Word-Program Operation The flash memory bank of the SST32HF20x/40x devices is programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program |
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