Time(200ns/div)

V

2V/div

ENABLE

V

2V/div

SENSE_OUT

TPS3895, TPS3896

TPS3897, TPS3898

SBVS172A

– JULY 2011 – REVISED SEPTEMBER 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

ENABLE POWER ON/OFF DELAY

(TPS3895P)

Figure 22.

THEORY OF OPERATION

GENERAL DESCRIPTION

The TPS3895, TPS3896, TPS3897, and TPS3898 devices (TPS389x) are a family of ultra-small supervisory

circuits. The TPS389x is designed to assert the SENSE_OUT or SENSE_OUT signal, as shown in Table 2 and

Table 3. When the SENSE pin rises above 0.5 V and the enable input is asserted (ENABLE = high or ENABLE =

low) , the output asserts (SENSE_OUT goes high or SENSE_OUT goes low) after the capacitor-adjustable delay

time. The SENSE pin can be set to any voltage threshold above 0.5 V using an external resistor divider. A broad

range of output delay times and voltage thresholds can be supported, allowing these devices to be used in wide

array of applications.

Table 2. TPS3895/7 Truth Table

CONDITIONS

OUTPUT

STATUS

ENABLE = high

SENSE

SENSE_OUT = low

Output not asserted

ENABLE = low

SENSE

SENSE_OUT = low

Output not asserted

ENABLE = low

SENSE

SENSE_OUT = low

Output not asserted

ENABLE = high

SENSE

SENSE_OUT = high

Output asserted after delay

Table 3. TPS3896/8 Truth Table

CONDITIONS

OUTPUT

STATUS

ENABLE = low

SENSE

SENSE_OUT = high

Output not asserted

ENABLE = high

SENSE

SENSE_OUT = high

Output not asserted

ENABLE = high

SENSE

SENSE_OUT = high

Output not asserted

ENABLE = low

SENSE

SENSE_OUT = low

Output asserted after delay

10

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