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TPS5420-Q1 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS5420-Q1 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 22 page Design Procedure DVIN = () IOUT(MAX) ×0.25 +IOUT(MAX) MAX ×ESR CBULK SW × ƒ (2) I CIN + I OUT(MAX) 2 (3) TPS5420-Q1 www.ti.com................................................................................................................................................... SLVS752B – NOVEMBER 2007 – REVISED JUNE 2008 The following design procedure can be used to select component values for the TPS5420. Alternately, the SWIFT Designer Software may be used to generate a complete design. The SWIFT Designer Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process. To begin the design process, a few parameters must be determined. The designer must know the following: • Input voltage range • Output voltage • Input ripple voltage • Output ripple voltage • Output current rating • Operating frequency Design Parameters For this design example, use the following as the input parameters: DESIGN PARAMETER(1) EXAMPLE VALUE Input voltage range 10 V to 36 V Output voltage 5 V Input ripple voltage 300 mV Output ripple voltage 30 mV Output current rating 2 A Operating frequency 500 kHz (1) As an additional constraint, the design is set up to be small size and low component height. Switching Frequency The switching frequency for the TPS5420 is internally set to 500 kHz. It is not possible to adjust the switching frequency. Input Capacitors The TPS5420 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The recommended value for the decoupling capacitor is 10 µF. A high-quality ceramic type X5R or X7R is required. For some applications, a smaller-value decoupling capacitor may be used, if the input voltage and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage, including ripple. For this design, two 4.7- µF capacitors, C1 and C4 are used to allow for smaller 1812 case size to be used while maintaining a 50-V rating. This input ripple voltage can be approximated by Equation 2 : Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CI is the input capacitor value, and ESRMAX is the maximum series resistance of the input capacitor. The maximum RMS ripple current also needs to be checked. For worst-case conditions, this is approximated by Equation 3: In this case, the calculated input ripple voltage is 118 mV, and the RMS ripple current is 1 A. The maximum voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitors are rated for 50 V, and the ripple current capacity for each is 3 A at 500 kHz, providing ample margin. The actual measured input ripple voltage may be larger than the calculated value, due to the output impedance of the input voltage source and parasitics associated with the layout. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TPS5420-Q1 |
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