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SST31LF041 Datasheet(PDF) 2 Page - Silicon Storage Technology, Inc |
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SST31LF041 Datasheet(HTML) 2 Page - Silicon Storage Technology, Inc |
2 / 26 page 2 Data Sheet 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 devices significantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST31LF041/041A/043/043A inherently use less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase or Program oper- ation is less than alternative flash technologies. The mono- lithic ComboMemory eliminates redundant functions when using two separate memories of similar architecture; there- fore, reducing the total power consumption. The SuperFlash technology provides fixed Erase and Pro- gram times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Pro- gram cycles. The SST31LF041/041A/043/043A devices also improve flexibility by using a single package and a common set of signals to perform functions previously requiring two sepa- rate devices. To meet high density, surface mount require- ments, the SST31LF041/043 device is offered in 40-lead TSOP package and the SST31LF041A/043A device is offered in 32-lead TSOP package. See Figures 1 and 2 for the pinouts. Device Operation The ComboMemory uses BES# and BEF# to control oper- ation of either the SRAM or the flash memory bank. Bus contention is eliminated as the monolithic device will not recognize both bank enables as being simultaneously active. If both bank enables are asserted (i.e., BEF# and BES# are both low), the BEF# will dominate while the BES# is ignored and the appropriate operation will be exe- cuted in the flash memory bank. SST does not recommend that both bank enables be simultaneously asserted. All other address, data, and control lines are shared which minimizes power consumption and area. The device goes into standby when both bank enables are raised to VIHC. See Table 3 for SRAM operation mode selection. For SST31LF041A/043A only: BES# and OE# share pin 32. During SRAM operation, pin 32 will function as BES#. During flash operation, pin 32 will function as OE#. When pin 32 (OE#/BES#) is high, the data bus is in high impedance state. SRAM Operation With BES# low and BEF# high, the SST31LF041/041A operate as a 128K x8 CMOS SRAM and the SST31LF043/043A operate as 32K x8 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SRAM is mapped into the first 128 KByte address space of the device for 041/041A or 32 KByte for 043/043A. Read and Write cycle times are equal. SRAM Read The SRAM Read operation of the SST31LF041/041A/ 043/043A are controlled by OE# and BES#, both have to be low with WE# high, for the system to obtain data from the outputs. BES# is used for SRAM bank selection. When BES# and BEF# are high, both memory banks are deselected. OE# is the output control and is used to gate data from the output pins. The data bus is in high imped- ance state when OE# is high. See Figure 3 for the Read cycle timing diagram. SRAM Write The SRAM Write operation of the SST31LF041/041A/043/ 043A is controlled by WE# and BES#; both have to be low for the system to write to the SRAM. BES# is used for SRAM bank selection. During the Byte-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The Write time is measured from the last falling edge to the first rising edge of BES# and WE#. OE# can be VIL or VIH, but no other value, for SRAM Write operations. See Figure 4 for the SRAM Write cycle timing diagram. Flash Operation With BEF# active, the SST31LF041/041A/043/043A oper- ate as a 512K x8 flash memory. The flash memory bank is read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and internally timed Erase and Program operations. See Table 3 for flash operation mode selection. Flash Read The Read operation of the SST31LF041/041A/043/043A devices are controlled by BEF# and OE#; both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are dese- lected and only standby power is consumed. OE# is the |
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