TMS464409, TMS464409P, TMS465409, TMS465409P

16 777 216 BY 4-BIT EXTENDED DATA OUT

DYNAMIC RANDOM-ACCESS MEMORIES

SMKS895A – MAY 1997 – REVISED OCTOBER 1997

6

POST OFFICE BOX 1443

hidden refresh

A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by

RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally.

CAS-before-RAS ( CBR ) refresh

The external address is ignored, and the refresh address is generated internally.

battery-backup refresh

A low-power battery-backup refresh mode that requires less than 250

mA of refresh current is available on the

TMS464409P and TMS465409P. Data integrity is maintained using CBR refresh with a period of 31.25

ms while

holding RAS low for less than 300 ns. To minimize current consumption, all input levels must be at LVCMOS

self-refresh (TMS46x409P)

The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both

held low for a minimum of 100

ms. The chip is then refreshed internally by an on-board oscillator. No external

address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode,

a full set of row addresses) must be executed before continuing with normal operation. The burst refresh

ensures the DRAM is fully refreshed.

power up

To achieve proper device operation, an initial pause of 200

µs followed by a minimum of eight initialization cycles

( RAS-only or CBR ) cycle.

test mode

The test mode (see Figure 1) is initiated with a CBR-refresh cycle while simultaneously holding the W input low.

The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or

write on subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test

mode if a CBR refresh cycle with W held high or a RAS-only refresh cycle is performed.

In the test mode, the device is configured as 1024K bits

× 4 bits for each DQ. Each DQ pin has a separate 4-bit

parallel read and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal

bits are compared for each DQ pin. If the four bits agree, DQ goes high; if not, DQ goes low. During a write cycle,

the data states of all four DQs must be the same to ensure proper function of the test mode. Test time is reduced

by a factor of four for this series.