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TLV70530YFPT Datasheet(PDF) 2 Page - Texas Instruments |
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TLV70530YFPT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 26 page TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS(1) PRODUCT VOUT XX(X) is nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example 28 = 2.8 V). TLV705xx(x)Pyyyz P is optional; devices with P have an LDO regulator with an active output discharge. YYY is Package Designator Z is Package Quantity; R is for Reel (3000 pieces), T is for Tape (250 pieces) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Specified at TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND. VALUE UNIT MIN MAX VIN –0.3 6 V Voltage(2) VEN –0.3 6 V VOUT –0.3 6 V Maximum output current IOUT Internally limited Output short-circuit duration Indefinite Continuous total power dissipation PDISS See Table 2 Operating junction, TJ –55 +150 °C Temperature Storage, Tstg –55 +150 °C Human body model (HBM) 2 kV QSS 009-105 (JESD22-A114A) Electrostatic Discharge Rating(3) Charged device model (CDM) 500 V QSS 009-147 (JESD22-C101B.01) (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. (2) All voltages are with respect to network ground terminal. (3) ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL INFORMATION TLV705 THERMAL METRIC(1) YFF, YFP UNITS 4 BALLS θJA Junction-to-ambient thermal resistance 160 θJCtop Junction-to-case (top) thermal resistance 80 θJB Junction-to-board thermal resistance 90 °C/W ψJT Junction-to-top characterization parameter 0.5 ψJB Junction-to-board characterization parameter 78 θJCbot Junction-to-case (bottom) thermal resistance N/A (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 2 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated |
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