TLV705

TLV705P

SBVS151B

– DECEMBER 2010 – REVISED DECEMBER 2011

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

XX(X) is nominal output voltage. For output voltages with a resolution of 100 mV, two digits

are used in the ordering number; otherwise, three digits are used (for example 28 = 2.8 V).

TLV705xx(x)Pyyyz

P is optional; devices with P have an LDO regulator with an active output discharge.

YYY is Package Designator

Z is Package Quantity; R is for Reel (3000 pieces), T is for Tape (250 pieces)

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

VALUE

UNIT

MIN

MAX

–0.3

6

V

–0.3

6

V

–0.3

6

V

Maximum output current

Internally limited

Output short-circuit duration

Indefinite

See Table 2

–55

+150

°C

Temperature

–55

+150

°C

Human body model (HBM)

2

kV

QSS 009-105 (JESD22-A114A)

Charged device model (CDM)

500

V

QSS 009-147 (JESD22-C101B.01)

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2)

All voltages are with respect to network ground terminal.

(3)

ESD testing is performed according to the respective JESD22 JEDEC standard.

THERMAL INFORMATION

TLV705

YFF, YFP

UNITS

4 BALLS

Junction-to-ambient thermal resistance

160

Junction-to-case (top) thermal resistance

80

Junction-to-board thermal resistance

90

°C/W

Junction-to-top characterization parameter

0.5

Junction-to-board characterization parameter

78

Junction-to-case (bottom) thermal resistance

N/A

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

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