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MAX5982A Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX5982A Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 17 page IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated 70W High-Power MOSFET 8 ______________________________________________________________________________________ Pin Description (continued) PIN NAME FUNCTION MAX5982A/ MAX5982B MAX5982C 11 11 2EC 2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is enabled at 2EC when a Type 2 PSE or a wall adapter is detected. When powered by a Type 2 PSE, the 2EC current sink is enabled after the isolation MOSFET is fully on until VIN drops below the UVLO threshold. 2EC is latched when powered by a Type 2 PSE until VIN drops below the reset threshold. 2EC also asserts when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. 2EC is not latched if asserted by WAD. The 2EC current sink is turned off when the device is in sleep mode. 12 12 CLS Classification Resistor Input. Connect a resistor (RCLS) from CLS to VSS to set the desired classification current. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification. 13 –– LED LED Driver Output. During sleep mode, LED sources a periodic current (ILED) at 250Hz with 25% duty cycle. The amplitude of ILED is set by RSL according to the formula ILED (in A) = 645.75/(RSL + 1200). 14 –– SL Sleep Mode Enable Input. In the MAX5982B, a falling edge on SL brings the device into sleep mode (VSL must drop below 0.75V). In the MAX5982A, VSL must remain below the threshold (0.75V) for a period of at least 6s after falling edge to bring the device into sleep mode. An external resistor (RSL) connected between SL and VSS sets the LED current (ILED). 15 –– WK Wake Mode Enable Input. WK has an internal 2.5kI pullup resistor to the internal 5V bias rail. A falling edge on WK brings the device out of sleep mode and into the normal operating mode (wake mode). 16 –– ULP Ultra-Low-Power Sleep Enable Input (in Sleep Mode). ULP has an internal 50kI pullup resistor to the internal 5V bias rail. A falling edge on SL in the MAX5982B (and a 6s period below the SL threshold in the MAX5982A) while ULP is asserted low enables ultra-low-power sleep mode. When ultra-low-power sleep mode is enabled, the power consumption of the device is reduced even lower than normal sleep mode to comply with ultra-low-power sleep power requirements while still supporting MPS. –– –– EP Exposed Pad. Do not use EP as an electrical connection to VSS. EP is internally connected to VSS through a resistive path and must be connected to VSS externally. To optimize power dissipation, solder the exposed pad to a large copper power plane. |
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