CPC5002GS datasheet(5/14 Pages) IXYS

Part #	CPC5002GS

Description	Dual High-Speed Open-Drain

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Manufacturer	IXYS [IXYS Corporation]

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INTEGRATED CIRCUITS DIVISION

CPC5002

R01

www.ixysic.com

5

1.9 Switching Specifications

1 Falling propagation delay can be reduced by increasing instantaneous LED current drive, typically by increasing C

FWD .

2 Rising propagation delay depends on R

PU , CL , and IF .

Increasing IF above 2 • ITH (by reducing RS) increases the rising propagation delay.

3 Propagation Delay Skew is the worst case difference propagation delay, High to Low and Low to High between the two channels of a CPC5002

when measured using the test circuit shown below, which is tuned for approximately even rising and falling delays.

1.10 Propagation Delay Test Circuit

Parameter

Conditions

Symbol

Min

Typ

Max

Units

Timing Specifications

Clock Frequency

ISINK=6mA, CL=20pF

fMAX

-10-

MHz

Propagation Delay

Output Falling 1, 3

IF=1.5mA, VDD=3.3V,

RPU=499, CL=20pF,

0.5VIN to 0.5VDD_OUT

tPHL

35

81

120

ns

Output Rising 2, 3

tPLH

35

81

120

Pulse Width Distortion: |tPLH - tPLH|

As per tPHL and tPLH

PWD

85

ns

Propagation Delay Skew 3

As per tPHL and tPLH

tPSK

-

50

ns

Output Fall Time, 90% to 10%

IF=1.5mA, VDD=3.3V,

RPU=499, CL=20pF

tf

10

15

-

ns

Common Mode Specifications

Common Mode Transient Immunity

VCM=20VP-P , VDD=3.3V, TA=25°C

VOUT = High

VOUT>2V

CMH

5-

-

kV/

s

VOUT = Low

VOUT<0.8V

CML

7-

-

2k

Ω

27pF

3.3V

R

PU

499

Ω

C

L

20pF

V

DD

V

OUT

½ CPC5002

I

F

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