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M391B5773CH0 Datasheet(PDF) 3 Page - Samsung semiconductor |
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M391B5773CH0 Datasheet(HTML) 3 Page - Samsung semiconductor |
3 / 37 page - 3 - datasheet DDR3 SDRAM Rev. 1.21 Unbuffered DIMM Table Of Contents 240pin Unbuffered DIMM based on 2Gb C-die 1. DDR3 Unbuffered DIMM Ordering Information............................................................................................................. 4 2. Key Features................................................................................................................................................................. 4 3. Address Configuration .................................................................................................................................................. 4 4. x64 DIMM Pin Configurations (Front side/Back side) ................................................................................................... 5 5. x72 DIMM Pin Configurations (Front side/Back side) ................................................................................................... 6 6. Pin Description ............................................................................................................................................................. 7 7. SPD and Thermal Sensor for ECC UDIMMs ................................................................................................................ 7 8. Input/Output Functional Description.............................................................................................................................. 8 8.1 Address Mirroring Feature....................................................................................................................................... 9 8.1.1. DRAM Pin Wiring Mirroring .............................................................................................................................. 9 9. Function Block Diagram:............................................................................................................................................... 10 9.1 2GB, 256Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................... 10 9.2 2GB, 256Mx72 ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) ............................................................ 11 9.3 4GB, 512Mx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................... 12 9.4 4GB, 512Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)........................................................... 13 10. Absolute Maximum Ratings ........................................................................................................................................ 14 10.1 Absolute Maximum DC Ratings............................................................................................................................. 14 10.2 DRAM Component Operating Temperature Range .............................................................................................. 14 11. AC & DC Operating Conditions................................................................................................................................... 14 11.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................ 14 12. AC & DC Input Measurement Levels .......................................................................................................................... 15 12.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 15 12.2 VREF Tolerances.................................................................................................................................................... 16 12.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 17 12.3.1. Differential Signals Definition ......................................................................................................................... 17 12.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 17 12.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 18 12.3.4. Differential Input Cross Point Voltage ............................................................................................................ 19 12.4 Slew Rate Definition for Single Ended Input Signals............................................................................................. 19 12.5 Slew rate definition for Differential Input Signals ................................................................................................... 19 13. AC & DC Output Measurement Levels ....................................................................................................................... 20 13.1 Single Ended AC and DC Output Levels............................................................................................................... 20 13.2 Differential AC and DC Output Levels ................................................................................................................... 20 13.3 Single-ended Output Slew Rate ............................................................................................................................ 20 13.4 Differential Output Slew Rate ................................................................................................................................ 21 14. DIMM IDD specification definition ............................................................................................................................... 22 15. IDD SPEC Table ......................................................................................................................................................... 24 16. Input/Output Capacitance ........................................................................................................................................... 26 17. Electrical Characteristics and AC timing ..................................................................................................................... 27 17.1 Refresh Parameters by Device Density................................................................................................................. 27 17.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 27 17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 27 17.3.1. Speed Bin Table Notes .................................................................................................................................. 30 18. Timing Parameters by Speed Grade .......................................................................................................................... 31 18.1 Jitter Notes ............................................................................................................................................................ 34 18.2 Timing Parameter Notes........................................................................................................................................ 35 19. Physical Dimensions................................................................................................................................................... 36 19.1 256Mbx8 based 256Mx64/x72 Module (1 Rank) - M378/91B5773CH0 ................................................................36 19.2 256Mbx8 based 512Mx64/x72 Module (2 Ranks) - M378/91B5273CH0 .............................................................. 37 |
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