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PDTC114EMB Datasheet(PDF) 3 Page - NXP Semiconductors |
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PDTC114EMB Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 11 page PDTC114EMB All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 21 June 2012 3 of 11 NXP Semiconductors PDTC114EMB NPN resistor-equipped transistor; R1 = 10 k Ω, R2 = 10 kΩ 5. Limiting values [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 10 V VI input voltage positive - 40 V negative - -10 V IO output current - 100 mA ICM peak collector current pulsed; tp ≤ 1 ms - 100 mA Ptot total power dissipation Tamb ≤ 25 °C [1] - 250 mW Tj junction temperature - 150 °C Tamb ambient temperature -65 150 °C Tstg storage temperature -65 150 °C FR4 PCB, standard footprint Fig 2. Power derating curve for DFN1006B-3 (SOT883B) Tamb (°C) -75 175 125 25 75 -25 006aad009 100 200 300 Ptot (mW) 0 |
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