LPC4076FBD144 datasheet(3/123 Pages) NXP

Part #	LPC4076FBD144

Description	32-bit ARM Cortex-M4 MCU; up to 512 kB flash, 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC; SPIFI

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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LPC408X_7X

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 17 September 2012

3 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

 Three SSP controllers with FIFO and multi-protocol capabilities. The SSP

interfaces can be used with the GPDMA controller.

 Three enhanced I2C-bus interfaces, one with a true open-drain output supporting

the full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two

with standard port pins. Enhancements include multiple address recognition and

monitor mode.

 I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

 CAN controller with two channels.

 Digital peripherals:

 SD/MMC memory card interface.

 Up to 165 General Purpose I/O (GPIO) pins depending on the packaging, with

configurable pull-up/down resistors, open-drain mode, and repeater mode. All

GPIOs are located on an AHB bus for fast access and support Cortex-M4

bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any

pin of ports 0 and 2 can be used to generate an interrupt.

 Two external interrupt inputs configurable as edge/level sensitive. All pins on port 0

and port 2 can be used as edge sensitive interrupt sources.

 Four general purpose timers/counters, with a total of eight capture inputs and ten

compare outputs. Each timer block has an external count input. Specific timer

events can be selected to generate DMA requests.

 Quadrature encoder interface that can monitor one external quadrature encoder.

 Two standard PWM/timer blocks with external count input option.

 One motor control PWM with support for three-phase motor control.

 Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a

dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered

backup registers, allowing system status to be stored when the rest of the chip is

powered off. Battery power can be supplied from a standard 3 V lithium button cell.

The RTC will continue working when the battery voltage drops to as low as 2.1 V.

An RTC interrupt can wake up the CPU from any reduced power mode.

 Event Recorder that can capture the clock value when an event occurs on any of

three inputs. The event identification and the time it occurred are stored in

registers. The Event Recorder is located in the RTC power domain and can

therefore operate as long as there is RTC power.

 Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal

oscillator, watchdog warning interrupt, and safety features.

 CRC Engine block can calculate a CRC on supplied data using one of three

standard polynomials. The CRC engine can be used in conjunction with the DMA

controller to generate a CRC without CPU involvement in the data transfer.

 Analog peripherals:

 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,

conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can

be used with the GPDMA controller.

 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA

support.

 Two analog comparators.

 Power control:

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Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	LPC4076FBD144	2Mb / 123P	32-bit ARM Cortex-M4 MCU; Rev. 1-17 September 2012

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