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DAC1003D160HW Datasheet(PDF) 8 Page - Integrated Device Technology

Part # DAC1003D160HW
Description  Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

DAC1003D160HW Datasheet(HTML) 8 Page - Integrated Device Technology

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DAC1003D160_3
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
8 of 18
Integrated Device Technology
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
ICCA
analog supply current
-
73
85
mA
Ptot
total power dissipation
fclk = 80 MHz;
fIOUT = fQOUT = 5 MHz
-
422
540
mW
Clock inputs (CLK and CLKN)
VI(cm)
common-mode input
voltage
-
1.65
-
V
Vi(dif)(p-p)
peak-to-peak differential
input voltage
-
1.0
-
V
Analog outputs (IOUT, IOUTN, QOUT and QOUTN)
IO(fs)
full-scale output current
differential outputs
4
-
20
mA
Ro
output resistance
[1] -
150
-
k
Co
output capacitance
[1] -
3
-
pF
Digital inputs (I0 to I9, Q0 to Q9 and GAPD)
VIL
LOW-level input voltage
DGND
-
0.3 VCCD V
VIH
HIGH-level input voltage
0.7 VCCD -
VCCD
V
IIL
LOW-level input current
VIL = 0.3 VCCD
-
5
-
A
IIH
HIGH-level input current
VIH = 0.7 VCCD
-
5
-
A
Reference voltage output (GAPOUT)
VGAPOUT
voltage on pin GAPOUT
-
1.31
-
V
IGAPOUT
current on pin GAPOUT
external voltage
-
1
-
A
VGAPOUT voltage variation on pin
GAPOUT
-
133
-
ppm/
C
Clock timing inputs (CLK and CLKN)
fclk
clock frequency
-
80
MHz
tw(clk)H
HIGH clock pulse width
5
-
-
ns
tw(clk)L
LOW clock pulse width
5
-
-
ns
Input timing (I0 to I9 and Q0 to Q9); see Figure 5
th(i)
input hold time
1.1
-
3.4
ns
tsu(i)
input set-up time
1.5
-
+0.7
ns
Output timing (IOUT, IOUTN, QOUT, QOUTN)
ts
settling time
to  0.5 LSB
[1] -
16
-
ns
Digital filter specification (FIR); order N = 42 see Figure 6 and 7 and Table 7
fdata
data rate
-
-
80
MHz
ripple(pb)
pass-band ripple
fdata/fclk; 0.005 dB attenuation
-
0.405
-
Bp
power bandwidth
fdata/fclk; 3 dB attenuation
-
0.479
-
stpb
stop-band attenuation
fdata/fclk = 0.6 dB to 1 dB
-
69
-
dB
td(grp)
group delay time
-
11 Tclk
-
ns
Analog signal processing
INL
integral non-linearity
-
0.2
-
LSB
DNL
differential non-linearity
-
0.1
-
LSB
Table 5.
Characteristics …continued
VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = 40 C to +85 C; typical values measured at
VCCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 C; dynamic parameters measured using output schematic given in
Figure 10; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit


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